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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体器件结构及其制造方法
    • US20120193798A1
    • 2012-08-02
    • US13129321
    • 2011-02-26
    • Huicai ZhongQingqing LiangZhijiong LuoHuilong Zhu
    • Huicai ZhongQingqing LiangZhijiong LuoHuilong Zhu
    • H01L23/48H01L23/482H01L21/768
    • H01L23/53276H01L21/76807H01L21/76843H01L21/76846H01L21/76847H01L21/76877H01L2221/1094H01L2924/0002H01L2924/00
    • The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
    • 半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。 该结构包括:其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层,其中在所述层间介质层中形成沟槽,所述沟槽包括并入的通孔沟槽和导电布线沟槽,并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层,其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。 其中,导电层包括由导电材料包围的导电材料和纳米管/线层。 该结构的导电层具有较好的导热性,导电性和较高的抗电迁移能力,能有效防止金属离子向外扩散。
    • 3. 发明申请
    • Semiconductor Substrate, Integrated Circuit Having the Semiconductor Substrate, and Methods of Manufacturing the Same
    • 半导体基板,具有半导体基板的集成电路及其制造方法
    • US20130200456A1
    • 2013-08-08
    • US13696995
    • 2011-11-29
    • Huilong ZhuZhijiong LuoHaizhou YinHuicai Zhong
    • Huilong ZhuZhijiong LuoHaizhou YinHuicai Zhong
    • H01L27/12H01L27/092H01L21/762
    • H01L27/12H01L21/743H01L21/762H01L21/84H01L27/092H01L27/1203H01L29/78648H01L2924/0002H01L2924/00
    • The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
    • 本发明涉及半导体衬底,具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括:半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层,其中,在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔,以穿透所述第二绝缘材料层,以将所述第一导电材料层与 第二导电材料层,每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。
    • 4. 发明授权
    • Semiconductor structure and method for manufacturing the same
    • 半导体结构及其制造方法
    • US08957481B2
    • 2015-02-17
    • US13379407
    • 2011-05-11
    • Huilong ZhuHuicai ZhongHaizhou YinZhijiong Luo
    • Huilong ZhuHuicai ZhongHaizhou YinZhijiong Luo
    • H01L21/70H01L27/12H01L21/8238H01L21/336H01L21/308H01L21/762H01L29/78H01L29/66
    • H01L21/3086H01L21/76224H01L21/76229H01L29/66636H01L29/7848
    • The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device.
    • 本申请公开了一种半导体结构及其制造方法。 与传统的形成触点的方法相比,本公开减少了接触电阻,并且避免了栅极和接触插塞之间的短路,同时简化了制造工艺,增加了集成密度并降低了制造成本。 根据本公开的制造方法,形成第二浅沟槽隔离件,其上表面高于源极/漏极区域的上表面。 由栅极的侧壁间隔物,第二浅沟槽隔离件的侧壁间隔件和源极/漏极区域的上表面限定的区域形成为接触孔。 通过用导电材料填充接触孔来形成触点。 该方法省略了用于提供接触孔的蚀刻步骤,这降低了制造成本。 通过形成与栅极自对准的触点,该方法避免了未对准并且提高了器件的性能,同时减少了器件的占地面积并降低了器件的制造成本。
    • 5. 发明授权
    • Semiconductor substrate for manufacturing transistors having back-gates thereon
    • 用于制造其上具有背栅的晶体管的半导体衬底
    • US08829621B2
    • 2014-09-09
    • US13696995
    • 2011-11-29
    • Huilong ZhuZhijiong LuoHaizhou YinHuicai Zhong
    • Huilong ZhuZhijiong LuoHaizhou YinHuicai Zhong
    • H01L21/70H01L27/12H01L21/84H01L27/092H01L21/74H01L21/762H01L29/786
    • H01L27/12H01L21/743H01L21/762H01L21/84H01L27/092H01L27/1203H01L29/78648H01L2924/0002H01L2924/00
    • The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
    • 本发明涉及半导体衬底,具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括:半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层,其中,在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔,以穿透所述第二绝缘材料层,以将所述第一导电材料层与 第二导电材料层,每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。
    • 6. 发明授权
    • Semiconductor structure and method for fabricating the same
    • 半导体结构及其制造方法
    • US08633522B2
    • 2014-01-21
    • US13062733
    • 2010-09-20
    • Huilong ZhuHaizhou YinZhijiong LuoHuicai Zhong
    • Huilong ZhuHaizhou YinZhijiong LuoHuicai Zhong
    • H01L29/78
    • H01L29/7834H01L21/76224H01L29/165H01L29/665H01L29/6653H01L29/66545H01L29/6659H01L29/66636H01L29/7848
    • A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.
    • 半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件,每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物,其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部 第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20120168881A1
    • 2012-07-05
    • US13142591
    • 2011-01-27
    • Haizhou YinHuicai ZhongHuilong ZhuZhijiong Luo
    • Haizhou YinHuicai ZhongHuilong ZhuZhijiong Luo
    • H01L29/772H01L21/28
    • H01L29/7846H01L21/76224H01L29/045H01L29/66545H01L29/6659H01L29/7833
    • The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
    • 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括:提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽,所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽,其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力,这提高了半导体器件的响应速度和性能。