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41. 发明授权

US6154386A Memory device having a wide data path 失效
标题翻译：具有宽数据路径的存储器件
公开(公告)号：US6154386A
公开(公告)日：2000-11-28
申请号：US98127
申请日：1998-06-16
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C5/06 , G11C7/18 , G11C11/4097
CPC分类号： G11C7/18 , G11C11/4097 , G11C5/06
摘要： A memory device includes a plurality of bit lines, with each bit line serving at least one respective memory cell. A plurality of input/output lines are connected and parallel to the bit lines. The input/output lines allow data to be placed upon or extracted from the bit lines. Because the I/O lines are positioned parallel, rather than perpendicular, to the bit lines, the surface area required to implement the memory device does not increase in proportion to the number of bit lines provided. Accordingly, a relatively wide data path can be implemented on the memory device without significantly increasing the amount of surface area.
摘要翻译：存储器件包括多个位线，每个位线用于至少一个相应的存储器单元。多个输入/输出线被连接并且与位线并联。输入/输出线允许将数据放置在位线上或从位线中提取。因为I / O线与位线平行而不是垂直定位，所以实现存储器件所需的表面积不会与所提供的位线数量成比例地增加。因此，可以在存储器设备上实现相对较宽的数据路径，而不会显着增加表面积的量。

42. 发明授权

US5970020A Controlling the set up of a memory address 有权
标题翻译：控制内存地址的设置
公开(公告)号：US5970020A
公开(公告)日：1999-10-19
申请号：US154664
申请日：1998-09-16
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C8/06 , G11C8/00
CPC分类号： G11C8/06
摘要： A circuit is provided for controlling the set up of a memory address. The circuit includes a first latch circuit for latching a first memory address in response to a first simultaneous occurrence of a predetermined value for an output enable signal and a predetermined value for a row address strobe signal. A second latch circuit is coupled to the first latch circuit. The second latch circuit receives the first memory address from the first latch circuit and latches the first row address thereafter for decoding. The first latch circuit can latch a second memory address in response to a second simultaneous occurrence of the predetermined value for the output enable signal and the predetermined value for the row address strobe signal, the second simultaneous occurrence occurring while the first row address is being decoded.
摘要翻译：提供用于控制存储器地址的建立的电路。电路包括用于响应于输出使能信号的预定值和行地址选通信号的预定值的第一同时出现而锁存第一存储器地址的第一锁存电路。第二锁存电路耦合到第一锁存电路。第二锁存电路从第一锁存电路接收第一存储器地址，然后锁存第一行地址进行解码。第一锁存电路可以响应于输出使能信号的预定值和行地址选通信号的预定值的第二同时出现而锁存第二存储器地址，在第一行地址被解码时发生第二同时发生。

43. 发明授权

US5745499A Supervoltage detection circuit having a multi-level reference voltage 失效
公开(公告)号：US5745499A
公开(公告)日：1998-04-28
申请号：US540915
申请日：1995-10-11
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C29/46 , G01R31/28
CPC分类号： G11C29/46
摘要： An integrated memory circuit is described which can be tested using both a burn-in test and an application specific test. The application specific test is initiated by providing a supervoltage on one of the integrated memory circuit external input pins. A reference voltage circuit is described for producing a variable or multi-level reference voltage used by a supervoltage detection circuit. If a burn-in test is being performed, the reference voltage is adjusted from a level used when the memory is not operating in a burn-in test mode. A multi-level reference voltage is provided to the supervoltage detection circuit, thereby, adjusting the supervoltage level needed to initiate an application specific test.

44. 发明授权

US5706238A Self current limiting antifuse circuit 失效
标题翻译：自限流反熔丝电路
公开(公告)号：US5706238A
公开(公告)日：1998-01-06
申请号：US783623
申请日：1997-01-14
申请人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien S. Luong , Brett Debenham , Kim M. Pierce
发明人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien S. Luong , Brett Debenham , Kim M. Pierce
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： An antifuse bank includes a bank of self-decoupling anti fuse circuits. The anti fuse circuits are programmed according to a pattern of address bits by blowing antifuses corresponding to bits of the address. The antifuses are blown by applying a high voltage across the antifuse. As each antifuse is blown, its resistance drops and current through the antifuse increases. The self-decoupling circuit detects the increased current flow and, when the anti fuse resistance is sufficiently low, limits current flow through the anti fuse. The antifuse thus does not load the high voltage source as other antifuses are blown.
摘要翻译：反熔丝库包括一组自去耦反熔丝电路。反熔丝电路根据地址位的模式通过吹出与地址的位相对应的反熔丝来编程。通过在反熔丝上施加高电压来吹制反熔丝。当每个反熔丝熔断时，其电阻下降，并且通过反熔丝的电流增加。自解耦电路检测到增加的电流，当反熔丝电阻足够低时，限制电流通过反熔丝。因此，反熔丝因其他反熔丝被吹制而不加载高压源。

45. 发明授权

US08908428B2 Voltage assisted STT-MRAM writing scheme 有权
标题翻译：电压辅助STT-MRAM写入方案
公开(公告)号：US08908428B2
公开(公告)日：2014-12-09
申请号：US13753350
申请日：2013-01-29
申请人： Adrian E. Ong , Vladimir Nikitin , Mohamad Towfik Krounbi
发明人： Adrian E. Ong , Vladimir Nikitin , Mohamad Towfik Krounbi
IPC分类号： G11C11/14 , G11C11/16 , H01L43/02 , H01L43/12
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1675 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： An embodiment includes a three terminal magnetic element for a semiconductor memory device. The magnetic element includes a reference layer; a free layer; a barrier layer disposed between the reference layer and the free layer; a first electrode; an insulating layer disposed between the electrode and the free layer; and a second electrode coupled to sidewalls of the free layer.
摘要翻译：实施例包括用于半导体存储器件的三端子磁性元件。磁性元件包括参考层; 自由层设置在参考层和自由层之间的阻挡层; 第一电极; 设置在电极和自由层之间的绝缘层; 以及耦合到所述自由层的侧壁的第二电极。

46. 发明授权

US08717052B2 Testing fuse configurations in semiconductor devices 失效
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US08717052B2
公开(公告)日：2014-05-06
申请号：US13206434
申请日：2011-08-09
申请人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： G01R31/3187
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.
摘要翻译：用于测试半导体器件的方法，系统和设备。半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路，以及包括保险丝的熔丝电路，并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

47. 发明授权

US08446788B2 Programmable memory repair scheme 有权
公开(公告)号：US08446788B2
公开(公告)日：2013-05-21
申请号：US12922425
申请日：2009-04-09
申请人： Adrian E. Ong , Fan Ho
发明人： Adrian E. Ong , Fan Ho
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/76 , G11C11/401 , G11C11/4085 , G11C29/027 , G11C29/04 , G11C29/12 , G11C29/4401 , G11C29/48 , G11C29/78 , G11C29/789 , G11C29/802 , G11C2229/743
摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

48. 发明授权

US08411497B2 Method and system for providing a magnetic field aligned spin transfer torque random access memory 有权
标题翻译：用于提供磁场对准的自旋转移转矩随机存取存储器的方法和系统
公开(公告)号：US08411497B2
公开(公告)日：2013-04-02
申请号：US12774703
申请日：2010-05-05
申请人： Adrian E. Ong , Xueti Tang
发明人： Adrian E. Ong , Xueti Tang
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/165 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1693 , G11C2207/002
摘要： A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.
摘要翻译：描述了一种用于提供磁存储器的方法和系统。该方法和系统包括提供磁存储单元，与磁存储单元耦合的位线，预设线和与磁存储单元耦合的字线。每个磁存储单元包括磁性元件。位线驱动通过磁存储单元的选定存储单元写入电流以写入所选择的存储单元。预设线驱动预设电流接近而不是通过选定的存储单元。预设电流产生磁场以使所选择的存储单元的磁性元件沿一个方向定向。字线允许所选存储单元进行写入。位线位于预设线和存储单元之间，或者预设线位于存储单元之间和位线的存储单元侧。

49. 发明申请

US20120020159A1 NON-VOLATILE STATIC RAM CELL CIRCUIT AND TIMING METHOD 有权
标题翻译：非挥发性静态RAM单元电路和时序方法
公开(公告)号：US20120020159A1
公开(公告)日：2012-01-26
申请号：US13011726
申请日：2011-01-21
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C14/00 , H01R43/00
CPC分类号： G11C14/0081 , G11C14/0063 , G11C14/0072 , G11C14/009 , Y10T29/49117
摘要： A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.
摘要翻译：一种非易失性静态随机存取存储器单元，包括耦合到第一和第二晶体管以及第一和第二非易失性存储单元的双稳态再生电路。使用方法包括在非易失性存储单元和双稳态再生电路之间直接传送互补数据位。或者，来自双稳态再生电路的补充数据可以在被传送到存储器单元列中的非易失性存储器单元之前由读出放大器和第二双稳态再生电路再生。双稳态再生电路可能被复位到地电位。使用从双稳态再生电路直接读出的非易失性SRAM单元的应用包括非易失性触发器或非易失性复用器。

50. 发明授权

US08063650B2 Testing fuse configurations in semiconductor devices 有权
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US08063650B2
公开(公告)日：2011-11-22
申请号：US12008318
申请日：2008-01-10
申请人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： G01R31/10 , G01R31/26
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.
摘要翻译：用于测试半导体器件的方法，系统和设备。半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路，以及包括保险丝的熔丝电路，并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

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