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41. 发明授权

US06271677B1 Semiconductor integrated circuit and method for testing the semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US06271677B1
公开(公告)日：2001-08-07
申请号：US09560126
申请日：2000-04-28
申请人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
发明人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
IPC分类号： H03K1900
CPC分类号： G01R31/318328
摘要： A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.
摘要翻译：半导体IC包括测试电路，其包括逻辑电路，测试定时发生器，用作测试信号生成点的第一寄存器，以及用作测试信号观测点的第二和第三寄存器。在该测试电路中，从逻辑电路中的多个信号传输路径选择要测试的目标信号传输路径，并且测试定时发生器输出具有根据所选信号传输路径的延迟时间的周期的测试时钟设计到第一至第三寄存器，由此第一寄存器产生测试信号，第二和第三寄存器观察测试信号。因此，连接测试信号生成点和测试信号观察点的信号传输路径被高效率地测试，由此对于执行测试次数较少的延迟故障来测试更多的信号传输路径。

42. 发明授权

US4752113A Waterproof optical fiber cable 失效
标题翻译：防水光缆
公开(公告)号：US4752113A
公开(公告)日：1988-06-21
申请号：US36454
申请日：1987-04-09
申请人： Yasunori Saito , Osamu Ichikawa , Toshio Oshima
发明人： Yasunori Saito , Osamu Ichikawa , Toshio Oshima
IPC分类号： H01B13/32 , G02B6/44
CPC分类号： G02B6/4427 , G02B6/4489 , G02B6/4491 , G02B6/4494
摘要： In a waterproof optical fiber cable for use in a communication system, one or more optical fibers are loosely put in grooves formed along a spacer and a plurality of filled portions are formed in each of said grooves by being filled with dampproof material with a predetermined interval so as to provide a plurality of filled portions and unfilled portions alternately, whereby undesired local bending of the optical fibers can be prevented. Also a method of making the waterproof optical fiber cable having such filled portions and unfilled portions is disclosed.

43. 发明授权

US4729627A Optical fiber cable for detecting low temperature 失效
标题翻译：用于检测低温的光缆
公开(公告)号：US4729627A
公开(公告)日：1988-03-08
申请号：US640093
申请日：1984-08-13
申请人： Yasunori Saito , Osamu Ichikawa
发明人： Yasunori Saito , Osamu Ichikawa
IPC分类号： G01K11/32 , G02B6/44 , H01J5/16
CPC分类号： G01K11/32
摘要： An optical fiber cable for detecting a low temperature comprising a center member made of a material having a low coefficient of linear expansion and one or more longitudinally extending grooves in each of which at least one optical fiber is placed, (i) wherein at least one optical fiber comprising a core and a cladding both made of silica glass is placed in each of said grooves and the interior space of the groove which is not occupied by the optical fiber or fibers may be filled with a resin which has a low glass transition temperature; or (ii) wherein each of the optical fibers placed in each of said grooves, have different coating structures from each other and/or different fiber structures from each other so as to detect a low temperature in different temperature ranges.
摘要翻译：一种用于检测低温的光缆，包括由具有低线性膨胀系数的材料制成的中心部件和一个或多个纵向延伸的凹槽，每个光纤放置至少一根光纤，（i）其中至少一个包括由石英玻璃制成的芯和包层的光纤被放置在每个所述凹槽中，并且未被光纤或纤维占据的槽的内部空间可以填充有玻璃化转变温度低的树脂 ; 或（ii）其中放置在每个所述凹槽中的每个光纤彼此具有不同的涂层结构和/或彼此不同的纤维结构，以便检测不同温度范围内的低温。

44. 发明授权

US08696342B2 Waveform monitor apparatus of injection molding machine 有权
标题翻译：注塑机波形监测仪
公开(公告)号：US08696342B2
公开(公告)日：2014-04-15
申请号：US13554259
申请日：2012-07-20
申请人： Nobukazu Kasuga , Hirofumi Murata , Takashi Hakoda , Osamu Ichikawa
发明人： Nobukazu Kasuga , Hirofumi Murata , Takashi Hakoda , Osamu Ichikawa
IPC分类号： B29C45/77 , B29C45/78
CPC分类号： B29C45/766 , B29C45/80 , B29C2045/7606 , B29C2945/76096 , B29C2945/76264 , B29C2945/76498 , B29C2945/76505 , B29C2945/76595 , B29C2945/76859
摘要： When a waveform monitor apparatus 1 of an injection molding machine M for monitoring an operation waveform at least during molding is configured by mounting the waveform monitor apparatus 1 on the injection molding machine M for performing molding according to a specific molding system, a parting opening detecting means Fp for detecting change data of a parting opening Lm to a time during molding, and an operation waveform displaying means Fd for displaying at least change data from a resin filling start is into a mold 2 to a cooling time termination to of the mold 2, detected by the parting opening detecting means Fp, on a waveform displaying portion 5 of a screen 4v on a display 4 attached to a molding machine controller 3 are provided.
摘要翻译：当至少在成型期间用于监视操作波形的注射成型机M的波形监视装置1通过将波形监视装置1安装在根据特定模制系统进行模制的注射成型机M上而构成时，意味着用于检测分模开口Lm到成型时间的变化数据的Fp，并且至少显示来自树脂填充开始的变化数据的操作波形显示装置Fd进入模具2到模具2的冷却时间终止提供了由分型开启检测装置Fp检测到的，在安装在成型机控制器3上的显示器4上的屏幕4v的波形显示部分5上。

45. 发明授权

US08431459B2 Semiconductor wafer, semiconductor device, and method of manufacturing a semiconductor device 有权
标题翻译：半导体晶片，半导体器件以及半导体器件的制造方法
公开(公告)号：US08431459B2
公开(公告)日：2013-04-30
申请号：US12934233
申请日：2009-03-26
申请人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
发明人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
IPC分类号： H01L21/00
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/205 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/78648 , H01L29/78681
摘要： It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.
摘要翻译：本发明的目的是使用实用和简单的方法在氧化物层和3-5族化合物半导体之间形成良好的界面。提供了包括第一半导体层的半导体晶片，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 和形成为与第一半导体层接触的第二半导体层是与InP晶格匹配或伪晶格匹配的组3-5化合物半导体层，并且可相对于第一半导体层选择性地氧化。还提供了一种半导体器件，其包括第一半导体层，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 通过相对于第一半导体层选择性地氧化形成为与第一半导体层接触的组3-5化合物的第二半导体层的至少一部分，并且晶格匹配或伪晶格匹配的InP形成的氧化物层 ; 以及将电场与形成在第一半导体层中的沟道相加的控制电极。

46. 发明授权

US07348595B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07348595B2
公开(公告)日：2008-03-25
申请号：US10828492
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G11C5/02
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

47. 发明授权

US07295028B2 Semiconductor integrated circuit and memory test method 有权
标题翻译：半导体集成电路和存储器测试方法
公开(公告)号：US07295028B2
公开(公告)日：2007-11-13
申请号：US11166345
申请日：2005-06-27
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G01R31/02
CPC分类号： G11C29/36 , G11C29/14 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.
摘要翻译：本发明提供一种半导体集成电路，即使在集成电路的内置自检电路的运算速度受到限制的情况下，能够以存储器的实际运行速度测试高速存储器。为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分，第二个时钟的反相时钟，用于生成测试数据。此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据，从而将测试数据作为测试数据输入存储器。第二个时钟的频率比第一个时钟的频率低四分之一或一半。

48. 发明申请

US20060099471A1 Fuel cell system 失效
标题翻译：燃料电池系统
公开(公告)号：US20060099471A1
公开(公告)日：2006-05-11
申请号：US11262010
申请日：2005-10-28
申请人： Osamu Ichikawa , Kuri Kasuya
发明人： Osamu Ichikawa , Kuri Kasuya
IPC分类号： H01M8/04
CPC分类号： H01M8/04029 , H01M8/04097 , H01M8/04164
摘要： A fuel cell system includes a fuel cell, a fluid passage for warming, a gas-liquid separator, a supply passage and a recirculating module. The fuel cell generates power with supply of a reaction gas. The gas-liquid separator separates moisture contained in an anode exhaust gas which is discharged from the fuel cell. The supply passage returns the anode exhaust gas, from which the moisture has been separated by the gas-liquid separator, to an inlet side of the reaction gas. The recirculating module mixes the anode exhaust gas, which is returned via the supply passage, with the reaction gas. The gas-liquid separator lies adjacent to the recirculating module, and the fluid passage for warming is disposed between the gas-liquid separator and the recirculating module.
摘要翻译：燃料电池系统包括燃料电池，用于加温的流体通道，气液分离器，供应通道和再循环模块。燃料电池通过反应气体的供给而发电。气液分离器分离从燃料电池排出的阳极废气中含有的水分。供给通道将由气液分离器分离的水分的阳极废气返回到反应气体的入口侧。再循环模块将通过供应通道返回的阳极废气与反应气体混合。气液分离器位于循环模块附近，用于加温的流体通道设置在气 - 液分离器和循环模块之间。

49. 发明授权

US07032196B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
公开(公告)号：US07032196B2
公开(公告)日：2006-04-18
申请号：US10828230
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G06F17/50 , H01L23/58 , G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

50. 发明申请

US20060005095A1 Semiconductor integrated circuit and memory test method 有权
标题翻译：半导体集成电路和存储器测试方法
公开(公告)号：US20060005095A1
公开(公告)日：2006-01-05
申请号：US11166345
申请日：2005-06-27
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/36 , G11C29/14 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.
摘要翻译：本发明提供一种半导体集成电路，即使在集成电路的内置自检电路的运算速度受到限制的情况下，能够以存储器的实际运行速度测试高速存储器。为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分，第二个时钟的反相时钟，用于生成测试数据。此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据，从而将测试数据作为测试数据输入存储器。第二个时钟的频率比第一个时钟的频率低四分之一或一半。

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