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    • 45. 发明授权
    • Gate-array type intergated circuit semiconductor device
    • 门阵列型中间电路半导体器件
    • US4984050A
    • 1991-01-08
    • US297628
    • 1989-01-13
    • Masaharu Kobayashi
    • Masaharu Kobayashi
    • H01L21/768H01L21/82H01L23/522H01L27/118
    • H01L27/11801H01L2924/0002Y10S257/903Y10S257/906
    • A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cells. A field insulating layer is also formed on the substrate, which is partially embedded in the major surface of the substrate and is formed entirely on a wiring channel forming portion of the substrate and selectively on the basic cell forming portion of the same to surround each of the impurity regions. An insulating film is formed on the field insulating layer. A wiring structure is provided, which includes mutual wirings formed of a first level conductive layer, internal wirings, and interconnecting wirings formed of a second level conductive layer higher than the first level conductive layer. Each of the mutual wirings is formed only on the insulating film formed on the wiring channel forming portion and is connected to the impurity regions through the interconnecting and internal wirings.
    • 门阵列型集成电路半导体器件包括半导体衬底,其基本单元形成部分形成有多个基本电路元件的杂质区域。 杂质区形成多个碱性电池。 场致绝缘层也形成在衬底上,该衬底被部分地嵌入衬底的主表面中,并且整体地形成在衬底的布线沟道形成部分上,并且选择性地在其基本单元形成部分上围绕 杂质区。 在场绝缘层上形成绝缘膜。 提供一种布线结构,其包括由第一层导电层,内部布线和由比第一层导电层高的第二层导电层形成的互连布线形成的互连。 每个相互配线仅形成在形成在布线沟道形成部分上的绝缘膜上,并且通过互连和内部布线连接到杂质区域。