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41. 发明授权

US08390496B2 System and method for common mode translation 有权
标题翻译：共模转换的系统和方法
公开(公告)号：US08390496B2
公开(公告)日：2013-03-05
申请号：US12710889
申请日：2010-02-23
申请人： Ayman A. Fayed , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayed , Russell Byrd , Baher Haroun
IPC分类号： H03M1/66
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
摘要翻译：用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路，以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号。计算经过滤波的输入信号和反馈量化信号之间的差异，以产生误差信号，测量误差信号，并用Σ-Δ噪声整形来补偿误差信号。共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压共模级别。

42. 发明授权

US08373504B2 Class D power amplifier 有权
标题翻译： D类功率放大器
公开(公告)号：US08373504B2
公开(公告)日：2013-02-12
申请号：US13106611
申请日：2011-05-12
申请人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
发明人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/267 , H03F2200/297
摘要： A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.
摘要翻译：提供D类功率放大器（PA）。 PA通常包括驱动器，输出电容器，匹配网络和消除电路。驱动器具有输入，输出和寄生电容，并且驱动器的输入被配置为接收互补的第一和第二射频（RF）信号，其中在来自第一和第二射频的连续脉冲之间存在自由间隔第二RF信号。输出电容器和消除电路各自耦合到驱动器的输出，使得消除电路至少在空闲间隔期间提供谐波恢复，并且匹配网络耦合到输出电容器。

43. 发明申请

US20130021208A1 LOOP ANTENNA 有权
标题翻译： LOOP天线
公开(公告)号：US20130021208A1
公开(公告)日：2013-01-24
申请号：US13189135
申请日：2011-07-22
申请人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
发明人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
IPC分类号： H01Q1/38
CPC分类号： H01Q7/00 , H01Q23/00
摘要： A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region. The second metallization layer is disposed over and is in electrical contact with the first, second, and third conductive regions of the first metallization layer, and the second metallization layer includes a second window region that is at least partially aligned with the first window region.
摘要翻译：提供环形天线。该装置包括基底，第一金属化层和第二金属化层。基板具有第一和第二馈电端子和接地端子。第一金属化层设置在衬底上，并且包括第一窗口导电区域，第一导电区域，第二导电区域和第三导电区域。第一导电区域设置在第一馈电端子上并与第一馈电端子电接触; 它也是基本圆形的并且位于第一窗口区域内。第二导电区域设置在第二馈电端子上并与第二馈电端子电接触; 它也基本上是圆形的并且位于第一窗口区域内。第三导电区域设置在接地端子之上并与接地端子电接触，并且第三导电区域基本上围绕第一窗口区域。第二金属化层设置在第一金属化层的第一，第二和第三导电区域之上并与第一金属化层的第一，第二和第三导电区域电接触，并且第二金属化层包括至少部分地与第一窗口区域对准的第二窗口区域。

44. 发明申请

US20120306678A1 Three-level digital-to-analog converter 有权
标题翻译：三电平数模转换器
公开(公告)号：US20120306678A1
公开(公告)日：2012-12-06
申请号：US13134301
申请日：2011-06-03
申请人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
发明人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
IPC分类号： H03M1/72
CPC分类号： H03M1/66 , H03M1/747 , H03M3/464
摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.
摘要翻译：一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。类似的技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件实现DAC。每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

45. 发明申请

US20120299797A1 HIGH IMPEDANCE SURFACE 有权
标题翻译：高阻抗表面
公开(公告)号：US20120299797A1
公开(公告)日：2012-11-29
申请号：US13116885
申请日：2011-05-26
申请人： James N. Murdock , Eunyoung Seok , Brian P. Ginsburg , Vijay B. Rentala , Srinath Ramaswamy , Baher Haroun
发明人： James N. Murdock , Eunyoung Seok , Brian P. Ginsburg , Vijay B. Rentala , Srinath Ramaswamy , Baher Haroun
IPC分类号： H01Q21/00 , H01Q1/00
CPC分类号： H01Q1/52 , H01Q9/0407 , H01Q15/008
摘要： An apparatus for emitting radiation is provided. The apparatus comprises an antenna formed on a substrate, and a high impedance surface (HIS). The HIS has a plurality of cells formed on the substrate that are arranged to form an array that substantially surrounds at least a portion of the antenna. Each cell generally includes a ground plane, first plate, second plate, and an interconnect. The ground plane is formed on the substrate, while the first plate (which is substantially rectangular) is formed over and coupled to the ground plane. The first plate for each cell is also arranged so as to form a first checkered pattern for the array. The second plate (which is substantially rectangular) is formed over and is substantially parallel to the first plate. The first and second plates are also substantially aligned with a central axis that extends generally perpendicular to the first and second plates hand have a interconnect formed therebetween. The second plate for each cell is also arranged so as to form a second checkered pattern for the array.
摘要翻译：提供了一种用于发射辐射的装置。该装置包括形成在基板上的天线和高阻抗表面（HIS）。 HIS具有形成在基板上的多个单元，其被布置成形成基本上围绕天线的至少一部分的阵列。每个单元通常包括接地平面，第一板，第二板和互连。接地平面形成在基板上，而第一板（其基本上是矩形的）形成在接地平面上并耦合到接地平面。每个单元的第一板也被布置成形成阵列的第一格子图案。第二板（其基本上是矩形的）形成在第一板上方并且基本上平行于第一板。第一和第二板也基本上与大致垂直于第一和第二板延伸的中心轴对准，手具有形成在它们之间的互连。每个单元的第二板也被布置成形成用于阵列的第二方格图案。

46. 发明授权

US08120425B2 System and method for common mode translation 有权
标题翻译：共模转换的系统和方法
公开(公告)号：US08120425B2
公开(公告)日：2012-02-21
申请号：US12710928
申请日：2010-02-23
申请人： Ayman A. Fayed , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayed , Russell Byrd , Baher Haroun
IPC分类号： H03F3/45
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
摘要翻译：用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路，以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号，计算经滤波的输入信号和反馈量化信号之间的差异以产生误差信号，测量误差信号，并用Σ-Δ噪声整形补偿误差信号。共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压共模级别。

47. 发明申请

US20110084771A1 Low Phase Noise Frequency Synthesizer 有权
标题翻译：低相位噪声频率合成器
公开(公告)号：US20110084771A1
公开(公告)日：2011-04-14
申请号：US12577168
申请日：2009-10-10
申请人： Krishnasawamy Nagaraj , Neeraj Nayak , Srinadh Madhavapeddi , Baher Haroun
发明人： Krishnasawamy Nagaraj , Neeraj Nayak , Srinadh Madhavapeddi , Baher Haroun
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1215 , H03B5/1243
摘要： Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.
摘要翻译：本文公开了用于低相位噪声频率合成器的各种装置和方法。例如，一些实施例提供了可用于低相位噪声频率合成器中的振荡器。该振荡器包括一个振荡电路，一个连接到该振荡电路的多个交叉耦合晶体管对，一个连接到多个交叉耦合晶体管对的电流源，以及至少一个连接到多个交叉耦合晶体管对的开关。开关适于激活多个交叉耦合晶体管对的子集，并且使多个交叉耦合晶体管对的另一子集失效，以使用多个交叉耦合晶体管对的激活子集来操作振荡器中的振荡电路晶体管对。

48. 发明申请

US20100148850A1 System And Method For Common Mode Translation 有权
标题翻译：共模翻译系统与方法
公开(公告)号：US20100148850A1
公开(公告)日：2010-06-17
申请号：US12710889
申请日：2010-02-23
申请人： Ayman A. Fayad , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayad , Russell Byrd , Baher Haroun
IPC分类号： H03K17/687
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
摘要翻译：用于连续时间Σ-Δ模数转换器的共模转换的系统和方法。一个实施例包括具有耦合到差分信号输入的RC网络的环路滤波器，耦合到环路滤波器的Gm-C /量化器/ DAC电路（GQD），耦合到GQD的信号输入的共模电平调整电路，以及耦合到GQD和共模电平调整电路的调谐电路。 GQD评估由RC网络提供的输入信号。计算经过滤波的输入信号和反馈量化信号之间的差异，以产生误差信号，测量误差信号，并用Σ-Δ噪声整形来补偿误差信号。共模电平调节电路将差分输入信号的共模电平改变为基本上等于期望的共模电平，并且调谐电路基于两者之间的差异向共模电平调整电路提供补偿电压共模级别。

49. 发明申请

US20050116850A1 CONTINUOUS TIME FOURTH ORDER DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：连续时间四分之三的SIGMA模拟数字转换器
公开(公告)号：US20050116850A1
公开(公告)日：2005-06-02
申请号：US10699585
申请日：2003-10-31
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/322 , H03M3/43 , H03M3/454
摘要： A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.
摘要翻译：提出了一种第四级ΔΣ模数转换器，包括在第一反馈回路中包括无源滤波器，量化器和数模转换器的无源Δ-Σ调制器和具有大增益的有源滤波器在被动Δ-Σ调制器周围的第二反馈环路中的因子。

50. 发明授权

US06614703B2 Method and system for configuring integrated systems on a chip 有权
标题翻译：在芯片上配置集成系统的方法和系统
公开(公告)号：US06614703B2
公开(公告)日：2003-09-02
申请号：US09760287
申请日：2001-01-12
申请人： Robert L. Pitts , Baher Haroun
发明人： Robert L. Pitts , Baher Haroun
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C29/789 , H03K19/1733
摘要： A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method comprising: storing a plurality of configuration data in the non-volatile memory and, providing power to the volatile memory. After providing power to the volatile memory, serially loading the configuration data into the registers of the volatile memory to configure the semiconductor device.
摘要翻译：一种用于配置具有多个寄存器和易失性存储器的非易失性存储器的集成电路芯片的方法，包括：将多个配置数据存储在非易失性存储器中，并向易失性存储器提供电力。在向易失性存储器供电之后，将配置数据串行地加载到易失性存储器的寄存器中以配置半导体器件。

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