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41. 发明授权

US5740449A Method and apparatus for managing interrupts in a data processing system 失效
标题翻译：用于管理数据处理系统中的中断的方法和装置
公开(公告)号：US5740449A
公开(公告)日：1998-04-14
申请号：US598537
申请日：1996-02-08
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F9/46 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

42. 发明授权

US08761208B2 Audio network system and method of detecting topology in audio signal transmitting system 有权
公开(公告)号：US08761208B2
公开(公告)日：2014-06-24
申请号：US13423122
申请日：2012-03-16
申请人： Peter Charles Eastty
发明人： Peter Charles Eastty
IPC分类号： H04J3/02 , H03M13/00
CPC分类号： H04L45/00
摘要： In an audio network system constructed from a main node and a plurality of satellite nodes each having a plurality of ports, the main node generates and transmits a main packet including audio signals of a plurality of channels. Each satellite node selects one of the plurality of ports in turn, and confirms whether the main packet arrives at the selected port every predetermined period or not. When the main packet arrives at the selected port every predetermined period, the main packet is received via the port by continuing selection of the port. In the case where reception of the main packet is lost, one is selected from the plurality of ports in turn, the operation to confirm arrival of the main packet is restarted, and another port at which the main packet arrives at the present stage is automatically found.

43. 发明申请

US20080272950A1 Analogue to Digital Conversion 失效
标题翻译：模拟数字转换
公开(公告)号：US20080272950A1
公开(公告)日：2008-11-06
申请号：US11911599
申请日：2006-03-21
申请人： Peter Charles Eastty , Nicholas George Tembe
发明人： Peter Charles Eastty , Nicholas George Tembe
IPC分类号： H03M1/60 , H03M1/12
CPC分类号： H03M1/187 , H03M1/188
摘要： An analog-to-digital conversion arrangement converting an input analog signal into an output digital representation. Two or more analog-to-digital conversion paths each applying a conversion mapping between input analog signal magnitudes and respective digital values generate an intermediate representation of the input analog signal, the conversion paths being operable to apply different respective conversion mappings. An output circuit combines the intermediate representations from at least two conversion paths to generate the output digital representation, the intermediate representations being combined according to a weighting dependent on the magnitude of the input analog signal. At least one of the conversion paths has an enhanced sensitivity mode appropriate to a range of magnitudes of the input signal that are below a threshold magnitude. Control logic inhibits operation in the enhanced sensitivity mode if the magnitude of the input analog signal exceeds the threshold magnitude.
摘要翻译：将输入模拟信号转换为输出数字表示的模数转换装置。每个在输入模拟信号幅度和相应数字值之间应用转换映射的两个或多个模数转换路径产生输入模拟信号的中间表示，转换路径可操作以应用不同的相应转换映射。输出电路组合来自至少两个转换路径的中间表示以产生输出数字表示，所述中间表示根据与所输入的模拟信号的幅度有关的加权来组合。至少一个转换路径具有适合于低于阈值大小的输入信号的幅度范围的增强灵敏度模式。如果输入模拟信号的幅度超过阈值幅度，则控制逻辑禁止增强灵敏度模式下的操作。

44. 发明授权

US07031479B2 Automation of signal processing apparatus 失效
公开(公告)号：US07031479B2
公开(公告)日：2006-04-18
申请号：US10213264
申请日：2002-08-05
申请人： Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： H04B1/00
CPC分类号： H04H60/04 , G11B27/031 , G11B27/10 , G11B2220/2512 , G11B2220/90
摘要： Signal processing apparatus is described in which at least two sets of automated signal processing functions are controlled by stored automation commands, at times dependent upon at least two respective timecode signals which may each be associated with a respective source signal supplied to the signal processing apparatus.

45. 发明授权

US6044223A Object code allocation in multiple systems 失效
标题翻译：多个系统中的对象代码分配
公开(公告)号：US6044223A
公开(公告)日：2000-03-28
申请号：US108103
申请日：1998-06-30
申请人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Christopher Michael McCulloch , Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： H03G3/02 , G06F9/50 , G06F15/80 , H03H17/00 , H03H17/02 , H04H60/04 , G06F9/45
CPC分类号： H04H60/04 , G06F9/5066
摘要： This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
摘要翻译：本发明涉及多处理器系统中对象代码的分配。特别地，公开了用于将信号处理指令有效地分配给大量并行信号处理单元阵列的技术。

46. 发明授权

US5881077A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US5881077A
公开(公告)日：1999-03-09
申请号：US845559
申请日：1997-04-24
申请人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , William Kentish , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F9/48 , G06F11/10 , G06F11/30 , G06F11/32 , G06F15/177 , G06F17/17 , G06F11/00
CPC分类号： G06F11/3072 , G06F11/10 , G06F17/17 , G06F11/327 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events. On receipt of an interrupt signal, the control processor reads the interrupt data in the third memory locations C to determine the event indicated by the interrupt signal.
摘要翻译：提供了一种用于在数据处理系统中产生中断信号的方法和装置，所述中断信号被提供给系统的控制处理器，以指示系统中多个预定事件中的任何一个发生。该方法和装置通过以下方式操作：根据要指示的事件将数据写入系统的多对存储器位置A，B的至少一个存储器位置，存储器位置A，B在系统为各自的事件; 从存储单元对A，B中读取数据; 处理从每对存储器位置A，B读取的数据，以产生指示相关联的事件是否已经发生的中断数据，并且如果发送中断信号到控制处理器; 并将对应于事件的中断数据写入相应的第三存储器位置C，在控制处理器中为所述事件预定义第三存储单元C. 在接收到中断信号时，控制处理器读取第三存储器位置C中的中断数据，以确定由中断信号指示的事件。

47. 发明授权

US5877971A Digital signal processing 失效
标题翻译：数字信号处理
公开(公告)号：US5877971A
公开(公告)日：1999-03-02
申请号：US947289
申请日：1997-10-07
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.
摘要翻译：数字信号处理（例如滤波）装置包括流水线数字信号处理装置，用于通过将输入样本与一组与滤波系数相关联的多个子集组合而从输入数字信号的输入样本产生输出数字信号的每个输出样本在输入数字信号的相应多个采样周期期间该输出采样; 以及系数产生装置，用于响应于滤波器控制信号的当前状态向信号处理装置提供滤波器系数集合。系数产生装置可操作以在输入数字信号的相应多个采样周期期间将每组滤波器系数的多个子集提供给信号处理装置。

48. 发明授权

US5802385A Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions 失效
标题翻译：阵列处理系统，每个处理器包括路由器，并且在响应延迟指令中选择性地延迟单个处理器的输入/输出
公开(公告)号：US5802385A
公开(公告)日：1998-09-01
申请号：US515837
申请日：1995-08-16
申请人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
发明人： Rodney Hugh Densham , Peter Charles Eastty , Conrad Charles Cooke
IPC分类号： G06F15/16 , G06F15/177 , G06F15/80 , H04H60/04 , G06F15/82
CPC分类号： H04H60/04
摘要： In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.
摘要翻译：一方面，本发明提供并行处理装置，其包括布置成同步操作的数据处理器阵列4和多个数据总线。每个数据处理器4具有用于在处理器4和相应的数据总线H，V之间传送数据的第一和第二I / O装置16H，16V，多个处理器4连接到每个数据总线H，V和每个处理器4 通过所述I / O装置16H，16V连接到不同的一对数据总线H，V。每个处理器4包括用于互连第一和第二I / O装置16H，16V的选择性可操作的路由装置32H，32V，以在连接到其之间的总线H，V之间传送数据。

49. 发明授权

US09203366B2 Audio processing 有权
标题翻译：音频处理
公开(公告)号：US09203366B2
公开(公告)日：2015-12-01
申请号：US12921869
申请日：2009-03-10
申请人： Peter Charles Eastty
发明人： Peter Charles Eastty
IPC分类号： H03G5/00 , H03G3/00 , H03H17/02
CPC分类号： H03G3/00 , H03G5/005 , H03H17/0294
摘要： A method of generating a desired shelving filter for audio data, the desired shelving filter having a low-corner frequency U and a high-corner frequency f2, wherein the difference between the gain of the frequency response of the desired shelving filter at f2 and the gain of the frequency response of the desired shelving filter at U is substantially equal to a non-zero desired amount, the method comprising: determining an order for a first shelving filter of a first predetermined type, wherein the low-corner frequency of the first shelving filter is U and the high-corner frequency of the first shelving filter is fΣ, determining, for a second shelving filter of a second predetermined type and of a predetermined order m, a frequency fz for the low-corner frequency of the second shelving filter and a frequency Z4 for the high-corner frequency of the second shelving filter, where h is at least fi, f4 is greater than f3, and f4 is at most fi, and forming the desired shelving filter as a filter combination of the first shelving filter and the second shelving filter; wherein fz, f4 and the order of the first shelving filter are determined such that difference between the gain of the frequency response of the filter combination at fe and the gain of the frequency response of the filter combination at fi is substantially equal to the desired amount.
摘要翻译：一种产生用于音频数据的期望的搁置滤波器的方法，所述期望的载频滤波器具有低角频率U和高角频率f2，其中期望的滤波器在f2的频率响应的增益与在U处的期望的搁置滤波器的频率响应的增益基本上等于非零的期望量，该方法包括：确定第一预定类型的第一搁架滤波器的顺序，其中第一预定类型的低角频率搁架过滤器为U，第一搁架过滤器的高角频率为f＆Sgr;对于第二预定类型和预定次序m的第二搁架滤波器，确定第二搁置滤波器的低角频率的频率fz 搁架过滤器和频率Z4用于第二搁架过滤器的高角频率，其中h至少为fi，f4大于f3，f4最多为fi，并形成所需的搁架过滤器第一上架过滤器和第二搁架过滤器的过滤器组合; 其中fz，f4和第一搁架滤波器的顺序被确定为使得滤波器组合在fe处的频率响应的增益与滤波器组合在f 1处的频率响应的增益之间的差异大致等于期望量。

50. 发明授权

US09025792B2 Determining a configuration for an audio processing operation 有权
标题翻译：确定音频处理操作的配置
公开(公告)号：US09025792B2
公开(公告)日：2015-05-05
申请号：US13519966
申请日：2010-10-07
申请人： Peter Charles Eastty
发明人： Peter Charles Eastty
IPC分类号： H03G5/00 , H04R3/06 , H04S7/00 , H04S3/00
CPC分类号： H04R3/06 , H04R2205/024 , H04S3/00 , H04S7/301
摘要： A computer-implemented method of determining a configuration for an audio processing operation, wherein the audio processing operation comprises a predetermined set of one or more audio processing sub-operations, each audio processing sub-operation being configurable with one or more respective configuration parameters, the method comprising: specifying the predetermined set of one or more audio processing sub-operations; specifying a target frequency response; and performing a convergent optimization process to determine a configuration for the audio processing operation that reduces a difference between the frequency response of the audio processing operation and the target frequency response, wherein the configuration comprises a respective value for each configuration parameter of each audio processing sub-operation.
摘要翻译：一种用于确定音频处理操作的配置的计算机实现的方法，其中所述音频处理操作包括预定的一个或多个音频处理子操作集合，每个音频处理子操作可配置有一个或多个相应的配置参数，该方法包括：指定一个或多个音频处理子操作的预定集合; 指定目标频率响应; 并且执行收敛优化处理以确定减少音频处理操作的频率响应与目标频率响应之间的差异的音频处理操作的配置，其中，所述配置包括每个音频处理子级的每个配置参数的相应值操作。

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