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41. 发明申请

US20060166433A1 Recessed collar etch for buried strap window formation without poly2 审中-公开
标题翻译：嵌入式套圈蚀刻用于掩埋带窗口形成而不具有poly2
公开(公告)号：US20060166433A1
公开(公告)日：2006-07-27
申请号：US11043756
申请日：2005-01-26
申请人： Min-Soo Kim , Jonathan Davis , Debra Arnold , Robert Fuller
发明人： Min-Soo Kim , Jonathan Davis , Debra Arnold , Robert Fuller
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10867
摘要： A method for manufacturing a trench capacitor with a reduced resistance in a buried strap window for use in a memory circuit such as a dynamic random access memory circuit may be realized by reducing the number of polysilicon layers that are deposited. The method includes the deposition of a collar material followed by a dry etch of the collar material. The collar material is etched away from the top region leaving a layer of collar material on the wall of the trench between the surface of the first polysilicon layer filling the bottom of the trench and the upper region where the collar material was removed. The second polysilicon layer may be deposited after the collar material has been etched for making contact to other devices.
摘要翻译：可以通过减少沉积的多晶硅层的数量来实现用于在诸如动态随机存取存储器电路的存储器电路中使用的掩埋带窗口中具有降低的电阻的沟槽电容器的方法。该方法包括沉积套环材料，然后对套环材料进行干蚀刻。从顶部区域蚀刻套环材料，在填充沟槽底部的第一多晶硅层的表面和去除套环材料的上部区域之间在沟槽壁上留下一层环形材料。在衬套材料被蚀刻以与其它器件接触之后，可以沉积第二多晶硅层。

42. 发明授权

US09343298B2 Metal-insulator-metal capacitor and method for manufacturing thereof 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US09343298B2
公开(公告)日：2016-05-17
申请号：US13245247
申请日：2011-09-26
申请人： Mihaela Ioana Popovici , Johan Swerts , Malgorzata Pawlak , Kazuyuki Tomida , Min-Soo Kim , Jorge Kittl , Sven Van Elshocht
发明人： Mihaela Ioana Popovici , Johan Swerts , Malgorzata Pawlak , Kazuyuki Tomida , Min-Soo Kim , Jorge Kittl , Sven Van Elshocht
IPC分类号： B05D5/12 , H01L21/02 , C23C16/40 , C23C16/455 , H01L49/02
CPC分类号： H01L21/02356 , C23C16/409 , C23C16/45529 , H01L21/02197 , H01L21/0228 , H01L21/02304 , H01L28/56
摘要： The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack.
摘要翻译：本公开提供了一种在半导体衬底上制造层叠层的方法。该方法包括：制备基板第一导电层; 并且通过ALD在所述导电层上产生一层次叠层，所述子堆叠中的至少一层是TiO 2层，所述子堆叠的其它层是具有适合于在所述子层叠层结晶时形成立方体钙钛矿相。通过热处理获得结晶。当用于金属 - 绝缘体 - 金属电容器时，层叠层可以提供改进的特性，因为TiO 2层存在于子层中。

43. 发明授权

US09116429B2 Resist underlayer polymer, resist underlayer composition including the same, and method of patterning using the same 有权
标题翻译：抗蚀剂底层聚合物，包含其的抗蚀剂底层组合物，以及使用其的图案化方法
公开(公告)号：US09116429B2
公开(公告)日：2015-08-25
申请号：US12886808
申请日：2010-09-21
申请人： Jee-Yun Song , Hwan-Sung Cheon , Sung-Wook Cho , Kyong-Ho Yoon , Min-Soo Kim , Seung-Bae Oh
发明人： Jee-Yun Song , Hwan-Sung Cheon , Sung-Wook Cho , Kyong-Ho Yoon , Min-Soo Kim , Seung-Bae Oh
IPC分类号： G03F7/09 , G03F7/11 , G03F7/30 , G03F7/36 , C08G61/02 , C08L65/00
CPC分类号： G03F7/091 , C08G61/02 , C08G2261/3424 , C08G2261/45 , C08G2261/76 , C08L65/00 , G03F7/11 , G03F7/30 , G03F7/36
摘要： A resist underlayer polymer, a resist underlayer composition including the same, and a method of patterning using the same, the resist underlayer polymer including a repeating unit represented by at least one of Chemical Formula 1 and Chemical Formula 2:
摘要翻译：抗蚀剂下层聚合物，含有该抗蚀剂下层聚合物的抗蚀剂下层组合物，以及使用其形成图案的方法，所述抗蚀剂下层聚合物包括由化学式1和化学式2至少之一表示的重复单元：

44. 发明授权

US09041047B2 Organic light emitting diode display and method for manufacturing the same 有权
标题翻译：有机发光二极管显示器及其制造方法
公开(公告)号：US09041047B2
公开(公告)日：2015-05-26
申请号：US13535283
申请日：2012-06-27
申请人： Valeriy Prushinskiy , Won-Sik Hyun , Heung-Yeol Na , Min-Soo Kim , Beohm-Rock Choi
发明人： Valeriy Prushinskiy , Won-Sik Hyun , Heung-Yeol Na , Min-Soo Kim , Beohm-Rock Choi
IPC分类号： H01L51/52
CPC分类号： H01L51/5259 , H01L51/5237 , H01L51/5246 , H01L51/56
摘要： An exemplary embodiment described technology relates generally to an organic light emitting diode (OLED) display and a manufacturing method thereof. The organic light emitting diode (OLED) display according to an exemplary embodiment includes: a substrate; an encapsulation member; an organic light emitting element between the substrate and the encapsulation member; a middle sealing member including one side disposed between the substrate and the encapsulation member and another side extended from the one side to be bent and enclosing an edge of the encapsulation member; a first sealant sealing and combining the one side of the middle sealing member and the substrate to each other; a second sealant sealing and combining the other side of the middle sealing member and the encapsulation member to each other; and a getter at the one side of the middle sealing member and the encapsulation member.
摘要翻译：所描述的技术的示例性实施方式一般涉及有机发光二极管（OLED）显示器及其制造方法。根据示例性实施例的有机发光二极管（OLED）显示器包括：基板; 封装件; 在所述基板和所述密封部件之间的有机发光元件; 中间密封构件，其包括设置在所述基板和所述封装构件之间的一侧，以及从所述弯曲的一侧延伸并包围所述密封构件的边缘的另一侧; 将第一密封剂密封并将中间密封构件的一侧与基板相互结合; 将第二密封剂密封并将中间密封构件的另一侧与封装构件相互结合; 以及位于中间密封构件和密封构件一侧的吸气剂。

45. 发明授权

US08954096B2 Method and apparatus for detecting insertion of SIM card in a portable terminal 有权
标题翻译：用于检测SIM卡在便携式终端中的插入的方法和装置
公开(公告)号：US08954096B2
公开(公告)日：2015-02-10
申请号：US13240044
申请日：2011-09-22
申请人： Gwang-Hui Lee , Min-Soo Kim
发明人： Gwang-Hui Lee , Min-Soo Kim
IPC分类号： H04B1/38 , G06K7/00
CPC分类号： G06K7/0021 , G06K7/0069
摘要： A method and apparatus for detecting insertion of a Subscriber Identity Module (SIM) card in a portable terminal are provided, in which a SIM card is inserted into a SIM card connector, and a controller continuously supplies an operating voltage to a predetermined pin of the SIM card connector, determines whether a voltage level of the predetermined pin of the SIM card connector changes in a predetermined pattern, and determines that the SIM card has been inserted into the SIM card connector if the voltage level of the predetermined pin of the SIM card connector changes in the predetermined pattern.
摘要翻译：提供了一种用于检测在便携式终端中插入用户识别模块（SIM）卡的方法和装置，其中将SIM卡插入到SIM卡连接器中，并且控制器将工作电压连续地提供给 SIM卡连接器确定SIM卡连接器的预定引脚的电压电平是否以预定模式改变，并且如果SIM卡的预定引脚的电压电平被确定为SIM卡已插入到SIM卡连接器中连接器以预定模式改变。

46. 发明授权

US08835278B2 Method for forming a buried dielectric layer underneath a semiconductor fin 有权
标题翻译：在半导体翅片下形成掩埋介质层的方法
公开(公告)号：US08835278B2
公开(公告)日：2014-09-16
申请号：US13885884
申请日：2011-11-16
申请人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
发明人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/115
CPC分类号： H01L21/76224 , H01L21/76208 , H01L21/76281 , H01L21/823431 , H01L27/11521
摘要： Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.
摘要翻译：公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

47. 发明申请

US20140074818A1 MULTIPLICATION-BASED METHOD FOR STITCHING RESULTS OF PREDICATE EVALUATION IN COLUMN STORES 有权
标题翻译：用于结合柱子预测评估结果的综合方法
公开(公告)号：US20140074818A1
公开(公告)日：2014-03-13
申请号：US13614625
申请日：2012-09-13
申请人： Ronald J. Barber , Min-Soo Kim , Jae Gil Lee , Sam S. Lightstone , Guy M. Lohman , Lin Qiao , Vijayshankar Raman , Richard S. Sidle
发明人： Ronald J. Barber , Min-Soo Kim , Jae Gil Lee , Sam S. Lightstone , Guy M. Lohman , Lin Qiao , Vijayshankar Raman , Richard S. Sidle
IPC分类号： G06F17/30
CPC分类号： G06F17/30498 , G06F17/30315 , G06F17/30324
摘要： A system joins predicate evaluated column bitmaps having varying lengths. The system includes a column unifier for querying column values with a predicate and generating an indicator bit for each of the column values that is then joined with the respective column value. The system also includes a bitmap generator for creating a column-major linear bitmap from the column values and indicator bits. The column unifier also determines an offset between adjacent indicator bits. The system also includes a converter for multiplying the column-major linear bitmap with a multiplier to shift the indicator bits into consecutive positions in the linear bitmap.
摘要翻译：系统连接具有不同长度的谓词评估列位图。该系统包括列统一器，用于使用谓词查询列值，并为每个列值生成指示符位，然后与各个列值相结合。该系统还包括位图生成器，用于从列值和指示符位创建列主要的线性位图。列统一器还确定相邻指示符位之间的偏移。该系统还包括用于将列主要线性位图与乘法器相乘的转换器，以将指示符位移动到线性位图中的连续位置。

48. 发明申请

US20140065794A1 Method for Forming a Buried Dielectric Layer Underneath a Semiconductor Fin 有权
标题翻译：在半导体翅片下形成掩埋电介质层的方法
公开(公告)号：US20140065794A1
公开(公告)日：2014-03-06
申请号：US13885884
申请日：2011-11-16
申请人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
发明人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76208 , H01L21/76281 , H01L21/823431 , H01L27/11521
摘要： Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.
摘要翻译：公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

49. 发明申请

US20130169515A1 FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：柔性显示装置及其制造方法
公开(公告)号：US20130169515A1
公开(公告)日：2013-07-04
申请号：US13472374
申请日：2012-05-15
申请人： Valeriy PRUSHINSKIY , Won-Sik Hyun , Hyong-Yeol Na , Min-Soo Kim , Mu-Gyeom Kim
发明人： Valeriy PRUSHINSKIY , Won-Sik Hyun , Hyong-Yeol Na , Min-Soo Kim , Mu-Gyeom Kim
IPC分类号： G09G3/20 , B05D5/06
CPC分类号： H01L51/5253 , G06F1/1652 , G09G2380/02 , H01L27/3244 , H01L51/004 , H01L51/0097 , H01L51/525 , H01L51/56 , H01L2251/5338 , H01L2251/558
摘要： A flexible display apparatus including: a first film including a first surface and a second surface that are opposite each other, and a first groove formed in the first surface, the first film having a first rigidity; a third film on the second surface of the first film; a fourth film facing the third film; an emission display unit between and encapsulated by the third film and the fourth film; and a second film on the fourth film and facing the first film, the second film having a second rigidity that is less than the first rigidity.
摘要翻译：一种柔性显示装置，包括：第一膜，其包括彼此相对的第一表面和第二表面;以及形成在所述第一表面中的第一槽，所述第一膜具有第一刚性; 在第一膜的第二表面上的第三膜; 第四部影片面向第三部电影; 在第三膜和第四膜之间并封装的发射显示单元; 以及在所述第四膜上的面向所述第一膜的第二膜，所述第二膜具有小于所述第一刚性的第二刚性。

50. 发明授权

US08456909B2 Nonvolatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08456909B2
公开(公告)日：2013-06-04
申请号：US13308972
申请日：2011-12-01
申请人： Ki-Hong Lee , Kwon Hong , Min-Soo Kim
发明人： Ki-Hong Lee , Kwon Hong , Min-Soo Kim
IPC分类号： G11C16/04
CPC分类号： H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： Provided are a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device. The nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to surround the columnar channel plug, a memory layer disposed between the word line and the columnar channel plug, a plurality of word line connection portions, each of the word line connection portions connecting ends of word lines of a common layer from among the plurality of word lines, and a plurality of word line extension portions extending from the word line connection portions.
摘要翻译：提供一种非易失性存储器件及其制造方法，其可以确保三维非易失性存储器件的结构稳定性。非易失性存储装置包括一个或多个柱状通道插头，多个字线和多个电介质层，交替堆叠以包围柱状通道插头，设置在字线和柱状通道插头之间的存储层，多个字每个字线连接部分从多个字线中连接公共层的字线的端部，以及从字线连接部分延伸的多个字线延伸部分。

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