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41. 发明授权

US08151051B2 Redundant solid state disk system via interconnect cards 有权
标题翻译：冗余固态磁盘系统通过互连卡
公开(公告)号：US08151051B2
公开(公告)日：2012-04-03
申请号：US12429105
申请日：2009-04-23
申请人： Lee Dale Cleveland , Seth David Lewis , Christopher William Mann , Andrew Dale Walls
发明人： Lee Dale Cleveland , Seth David Lewis , Christopher William Mann , Andrew Dale Walls
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F11/2089 , G06F11/1441 , G06F11/2056
摘要： A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.
摘要翻译：配置第一互连卡，其中第一控制器包括在第一互连卡中。配置了耦合到第一互连卡的第二互连卡，其中第二控制器被包括在第二互连卡中。响应于包括在第一互连卡中的第一控制器的故障，通过包括在第二互连卡中的第二控制器来控制第一互连卡。响应于包括在第二互连卡中的第二控制器的故障，通过包括在第一互连卡中的第一控制器来控制第二互连卡。

42. 发明授权

US07538560B2 System and method for component failure protection 失效
标题翻译：组件故障保护的系统和方法
公开(公告)号：US07538560B2
公开(公告)日：2009-05-26
申请号：US11683352
申请日：2007-03-07
申请人： David Frank Hepner , Andrew Dale Walls
发明人： David Frank Hepner , Andrew Dale Walls
IPC分类号： G01R31/08
CPC分类号： G01R31/317 , G01R31/30 , G01R31/31704 , G01R31/31721
摘要： A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.
摘要翻译：提出了一种用于组件故障保护的系统和方法。在一个实施例中，系统包括被配置为在第一操作状态下操作的操作电路，其中第一操作状态接近电路故障阈值。另外，系统可以包括被配置为模拟操作电路的操作特性的金丝雀电路，其中金丝雀电路被配置为在第二操作状态下操作，并且其中第二操作状态更靠近电路故障阈值，接近第一个操作状态。该系统还可以包括耦合到操作电路和金丝雀电路的可变输入控制，其中可变输入控制被配置为监视第二操作状态，并且基于第二操作状态的接近度调整到操作电路的输入电路故障阈值。

43. 发明申请

US20080218916A1 SYSTEM AND METHOD FOR COMPONENT FAILURE PROTECTION 失效
标题翻译：用于组件故障保护的系统和方法
公开(公告)号：US20080218916A1
公开(公告)日：2008-09-11
申请号：US11683352
申请日：2007-03-07
申请人： David Frank Hepner , Andrew Dale Walls
发明人： David Frank Hepner , Andrew Dale Walls
IPC分类号： H02H3/00
CPC分类号： G01R31/317 , G01R31/30 , G01R31/31704 , G01R31/31721
摘要： A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.
摘要翻译：提出了一种用于组件故障保护的系统和方法。在一个实施例中，系统包括被配置为在第一操作状态下操作的操作电路，其中第一操作状态接近电路故障阈值。另外，系统可以包括被配置为模拟操作电路的操作特性的金丝雀电路，其中金丝雀电路被配置为在第二操作状态下操作，并且其中第二操作状态更靠近电路故障阈值，接近第一个操作状态。该系统还可以包括耦合到操作电路和金丝雀电路的可变输入控制，其中可变输入控制被配置为监视第二操作状态，并且基于第二操作状态的接近度调整到操作电路的输入电路故障阈值。

44. 发明授权

US07281142B2 Apparatus, system, and method for securely providing power supply commands 失效
标题翻译：用于安全地提供电源指令的装置，系统和方法
公开(公告)号：US07281142B2
公开(公告)日：2007-10-09
申请号：US10935587
申请日：2004-09-07
申请人： Carl Evan Jones , Robert Akira Kubo , Gregg Steven Lucas , Andrew Dale Walls
发明人： Carl Evan Jones , Robert Akira Kubo , Gregg Steven Lucas , Andrew Dale Walls
IPC分类号： G06F1/00
CPC分类号： G06F21/81 , G06F1/3203
摘要： An apparatus, system, and method are disclosed for securely providing power supply commands. A security feature is added to the remote management of power-on and power-off sequences. The feature allows for multiple controller nodes to receive a command to initiate a power sequence. Each controller node possesses a unique identifier. The nodes compare the received command with received commands of other nodes to confirm that each node received identical power commands. The security feature prevents inadvertent power commands from being received and executed by a single controller node. The unique identifier of each node must be provided before execution of the power command occurs.
摘要翻译：公开了用于安全地提供电源命令的装置，系统和方法。一个安全功能被添加到远程管理上电和关机序列。该功能允许多个控制器节点接收启动电源序列的命令。每个控制器节点具有唯一的标识符。节点将接收到的命令与其他节点的接收命令进行比较，以确认每个节点接收到相同的功率命令。安全功能可防止单个控制器节点接收和执行无意的电源命令。必须在执行电源命令之前提供每个节点的唯一标识符。

45. 发明授权

US06606677B1 High speed interrupt controller 失效
标题翻译：高速中断控制器
公开(公告)号：US06606677B1
公开(公告)日：2003-08-12
申请号：US09520876
申请日：2000-03-07
申请人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
发明人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.
摘要翻译：提供了一种用于数据通信系统的高速中断控制器和中断识别方案，可用于数据通信系统的子系统。控制器及其方案可以用于扩展有效接收和鉴别具有有限数量的中断输入线的处理器的中断数量。本发明可用于优化具有多个主机的共享总线内的数据管理，其中共享总线连接到多个总线主机和对应的从机，并且位于连接到系统处理器的外部总线与内部总线连接到内部处理器。该架构利用具有多个中断线的电路的高速中断控制器装置，并且可以具有位于设备中断处理器中的一个输出线和控制代码。该电路由一个状态寄存器组成，当外部中断源设备接收到一个中断时，该位置位适当位，中断屏蔽寄存器使能和禁止某些中断。控制代码用于监控和控制电路并为处理器接收的中断服务。

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