专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20120110247A1 MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE 有权
标题翻译：闪存高速缓存架构中的高速缓存存储器管理
公开(公告)号：US20120110247A1
公开(公告)日：2012-05-03
申请号：US13280869
申请日：2011-10-25
申请人： Evangelos Stavros Eleftheriou , Robert Haas , Xiao-Yu Hu
发明人： Evangelos Stavros Eleftheriou , Robert Haas , Xiao-Yu Hu
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246
摘要： A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.
摘要翻译：一种用于在闪存缓存架构中管理高速缓冲存储器的方法。该方法包括提供存储高速缓存控制器，至少包括闪存控制器的闪速存储器，以及至少后端存储设备，并且维护读取高速缓存元数据，用于跟踪要读取的闪速存储器缓存的数据，以及写入用于跟踪的高速缓存元数据闪存数据预计将被缓存。

42. 发明授权

US08799561B2 Valid page threshold based garbage collection for solid state drive 有权
标题翻译：基于固态驱动器的基于页面阈值的垃圾回收
公开(公告)号：US08799561B2
公开(公告)日：2014-08-05
申请号：US13560065
申请日：2012-07-27
申请人： Werner Bux , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Werner Bux , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0253 , G06F12/0261 , G06F2212/7205
摘要： A method for garbage collection in a solid state drive (SSD) includes determining whether the SSD is idle by a garbage collection module of the SSD; based on determining that the SSD is idle, determining a victim block from a plurality of memory blocks of the SSD; determining a number of valid pages in the victim block; comparing the determined number of valid pages in the victim block to a valid page threshold; and based on the number of valid pages in the victim block being less than the valid page threshold, issuing a garbage collection request for the victim block.
摘要翻译：一种在固态硬盘（SSD）中进行垃圾收集的方法，包括：通过SSD的垃圾收集模块确定SSD是否空闲; 基于确定所述SSD是空闲的，从所述SSD的多个存储块中确定受害者块; 确定受害者块中的有效页数; 将确定的受害者块中的有效页面数量与有效页面阈值进行比较; 并且基于受害者块中的有效页面的数量小于有效页面阈值，向受害者块发布垃圾回收请求。

43. 发明授权

US08977894B2 Operating a data storage system 有权
标题翻译：操作数据存储系统
公开(公告)号：US08977894B2
公开(公告)日：2015-03-10
申请号：US13387740
申请日：2010-08-05
申请人： Evangelos Stavros Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Evangelos Stavros Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G06F11/00 , G06F3/06 , G06F12/02
CPC分类号： G06F3/0647 , G06F3/0616 , G06F3/0688 , G06F12/0246 , G06F2212/7208 , G06F2212/7211
摘要： A data storage system including at least one memory device array including memory devices for storing data; and a storage subsystem controller for performing a method for operating the memory devices within the memory device array by relocating parity entities from a first memory device to a spare memory device replacing a failed memory device, and by storing one or more of reconstructed data entities on the first memory device.
摘要翻译：一种数据存储系统，包括至少一个存储器件阵列，其包括用于存储数据的存储器件; 以及存储子系统控制器，用于通过将奇偶校验实体从第一存储器设备重新定位到替换故障存储器设备的备用存储器设备，以及通过将一个或多个重构数据实体存储在存储设备阵列中来执行操作存储器设备的方法第一个存储设备。

44. 发明申请

US20130124794A1 LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES 有权
标题翻译：在包含固态存储器件的存储系统中逻辑地址映射
公开(公告)号：US20130124794A1
公开(公告)日：2013-05-16
申请号：US13812377
申请日：2011-07-25
申请人： Werner Bux , Robert Haas , Xiao-Yu Hu , Roman Pletka
发明人： Werner Bux , Robert Haas , Xiao-Yu Hu , Roman Pletka
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0848 , G06F12/0866 , G06F2212/214 , G06F2212/221 , G06F2212/222 , G06F2212/466 , G06F2212/7201
摘要： The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
摘要翻译：本想法提供了从/到固态存储器件的高读/写性能。控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。相反，这样的表被存储在存储器设备本身中，并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目，而不需要在闪存设备中更新存储这样的条目的相关闪存页面。通过这种设计，读取高速缓存可以有利地存储在DRAM上，即使没有掉电保护，而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

45. 发明授权

US09256527B2 Logical to physical address mapping in storage systems comprising solid state memory devices 有权
标题翻译：在包含固态存储器件的存储系统中的逻辑到物理地址映射
公开(公告)号：US09256527B2
公开(公告)日：2016-02-09
申请号：US13812377
申请日：2011-07-25
申请人： Werner Bux , Robert Haas , Xiao-Yu Hu , Roman Pletka
发明人： Werner Bux , Robert Haas , Xiao-Yu Hu , Roman Pletka
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0848 , G06F12/0866 , G06F2212/214 , G06F2212/221 , G06F2212/222 , G06F2212/466 , G06F2212/7201
摘要： The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
摘要翻译：本想法提供了从/到固态存储器件的高读/写性能。控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。相反，这样的表被存储在存储器设备本身中，并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目，而不需要在闪存设备中更新存储这样的条目的相关闪存页面。通过这种设计，读取高速缓存可以有利地存储在DRAM上，即使没有掉电保护，而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

46. 发明申请

US20090245519A1 RENEWAL MANAGEMENT FOR DATA ITEMS 失效
标题翻译：数据项目的再生管理
公开(公告)号：US20090245519A1
公开(公告)日：2009-10-01
申请号：US12411791
申请日：2009-03-26
申请人： Christian Cachin , Patrick Droz , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Rene A. Pawlitzek
发明人： Christian Cachin , Patrick Droz , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Rene A. Pawlitzek
IPC分类号： H04L9/06 , G06F17/30 , G06F12/14
CPC分类号： H04L9/0891 , G06F11/1461 , G06F21/6209 , G06F2221/2151
摘要： A system, method apparatus, and computer readable medium for managing renewal of a dynamic set of data items. Each data item has an associated renewal deadline, in a data item management system. A renewal schedule allocates to each data item a renewal interval for renewal of the data item. On addition of a new data item, if a potential renewal interval having a duration required for renewal of the data item, and having an ending at the renewal deadline for that item does not overlap a time period in the schedule during which the system is busy, the renewal schedule is automatically updated by allocating the potential renewal interval to the new data item. If the potential renewal interval does overlap a busy period, the renewal schedule is automatically updated by selecting an earlier renewal interval for at least one data item in the set.
摘要翻译：一种用于管理动态数据项集的更新的系统，方法装置和计算机可读介质。在数据项管理系统中，每个数据项具有关联的更新期限。更新计划为每个数据项分配更新数据项的更新间隔。在添加新数据项时，如果具有更新数据项所需的持续时间并且在该项目的更新期限结束的潜在更新间隔与系统正忙的时间表中的时间段不重叠，通过将潜在的更新间隔分配给新的数据项来自动更新更新计划。如果潜在的更新间隔与繁忙期间重叠，则通过为集合中的至少一个数据项选择较早的更新间隔来自动更新更新计划。

47. 发明授权

US08458568B2 Systems and methods for memory devices 失效
标题翻译：存储器件的系统和方法
公开(公告)号：US08458568B2
公开(公告)日：2013-06-04
申请号：US12889692
申请日：2010-09-24
申请人： Roy D. Cideciyan , Xiao-Yu Hu
发明人： Roy D. Cideciyan , Xiao-Yu Hu
IPC分类号： H03M13/00 , G11C29/00 , H04L1/00 , H03M13/35 , G06F11/10
CPC分类号： H04L1/0009 , G06F11/1048 , G06F11/1068 , G06F12/0246 , G06F2212/401 , G06F2212/403 , G06F2212/7202 , G06F2212/7207 , G11C7/1006 , G11C2029/0411 , G11C2207/102 , H03M13/35 , H04L1/0057
摘要： A method for writing data to a memory array includes receiving a write request including data from a processor, compressing the data, assigning a page strength to the compressed data, the page strength defined by a compression ratio used to compress the data, generating a parity data block associated with the compressed data, and saving the compressed data and the parity data block in a page of the memory array, the page of the memory array having a page strength corresponding to the assigned page strength of the compressed data.
摘要翻译：一种将数据写入存储器阵列的方法包括接收包括来自处理器的数据的写入请求，压缩数据，分配压缩数据的页面强度，由用于压缩数据的压缩比定义的页面强度，产生奇偶性与压缩数据相关联的数据块，以及将压缩数据和奇偶校验数据块保存在存储器阵列的页面中，存储器阵列的页面具有与所分配的压缩数据的页面强度对应的页面强度。

48. 发明申请

US20110138103A1 INTRA-BLOCK MEMORY WEAR LEVELING 失效
标题翻译：内存记忆磨损
公开(公告)号：US20110138103A1
公开(公告)日：2011-06-09
申请号：US12630991
申请日：2009-12-04
申请人： IIias IIiadis , Theodoros A. Antonakopoulos , Roman Pletka , Xiao-Yu Hu , Roy D. Cideciyan
发明人： IIias IIiadis , Theodoros A. Antonakopoulos , Roman Pletka , Xiao-Yu Hu , Roy D. Cideciyan
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F3/0616 , G06F3/064 , G06F3/0679 , G06F2212/7211
摘要： A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.
摘要翻译：在具有多个存储单元的固态存储器内部进行具有多个存储单元的固态存储器内的块内损耗均衡的方法包括以非均匀方式写入多个存储单元中的至少某些存储单元的步骤，在块内级别平衡固态存储器内的多个存储单元中的至少某些存储器单元的磨损。例如，如果多个存储器单元中的至少一些存储器单元的行为没有被表征，则该方法可以包括表征多个存储器单元中的至少一些的行为，并写入多个存储器中的至少某些存储器基于表征的行为，并且以不均匀的方式。

49. 发明授权

US08321762B2 Method for creating an error correction coding scheme 有权
标题翻译：用于创建纠错编码方案的方法
公开(公告)号：US08321762B2
公开(公告)日：2012-11-27
申请号：US12129778
申请日：2008-05-30
申请人： Ajay Dholakia , Evangelos Eleftheriou , Xiao-Yu Hu , Ilias Iliadis
发明人： Ajay Dholakia , Evangelos Eleftheriou , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , H03M13/036 , H03M13/17 , H03M13/19
摘要： The present invention relates to a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further comprises a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result.
摘要翻译：本发明涉及一种用于减少数据丢失的方法，包括：第一计算步骤，用于通过处理在至少两个主对角线上的给定数据集的分别相关联的数据信息实体来计算冗余集的每个冗余信息实体的中间结果表示纠错编码方案的奇偶校验矩阵。该方法还包括第二计算步骤，用于根据各自的中间结果来计算相应的冗余信息实体的信息内容。

50. 发明授权

US07926974B2 Light-guiding module and LED lamp using the same 失效
标题翻译：导光模块和LED灯使用相同
公开(公告)号：US07926974B2
公开(公告)日：2011-04-19
申请号：US12331394
申请日：2008-12-09
申请人： Shih-Hsun Wung , Yong-Dong Chen , Xiao-Yu Hu
发明人： Shih-Hsun Wung , Yong-Dong Chen , Xiao-Yu Hu
IPC分类号： F21V1/06
CPC分类号： F21V29/763 , F21K9/00 , F21V29/004 , F21V29/75 , F21V29/76 , F21V29/85 , F21Y2115/10
摘要： An LED lamp includes a heat sink, a plurality of LED modules mounted on a top of the heat sink and a plurality of light-guiding modules respectively fixed on the LED modules. The heat sink includes a base and a plurality of fins extending downwardly from the base. Each LED module includes a plurality of LEDs mounted thereon. Each light-guiding module includes a mounting bracket defining a plurality of through holes therein and a plurality of guiding units respectively received in the through holes of the mounting bracket. The guiding units are respectively in alignment with the LEDs of a corresponding LED module and receive the LEDs in lower ends thereof to reflect and guide light generated by the corresponding LED module in a predetermined manner.
摘要翻译： LED灯包括散热器，安装在散热器顶部的多个LED模块和分别固定在LED模块上的多个导光模块。散热器包括底座和从基座向下延伸的多个翅片。每个LED模块包括安装在其上的多个LED。每个导光模块包括在其中限定多个通孔的安装支架和分别容纳在安装支架的通孔中的多个引导单元。引导单元分别与相应的LED模块的LED对准，并在其下端接收LED，以预定的方式反射和引导由对应的LED模块产生的光。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式