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41. 发明申请

US20050289440A1 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US20050289440A1
公开(公告)日：2005-12-29
申请号：US10879262
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在本发明的一个实施例中，包括用于控制存储器子系统中的纠错码（ECC）算法的应用的可执行指令的计算机可读介质包括用于记录从存储器子系统检索的数据中的数据损坏的发生的代码，分析数据损坏的发生以检测在存储器子系统的不同地址之间的数据损坏的重复位模式;以及用于控制ECC算法的应用以擦除与由用于分析的代码检测的重复位模式相关联的位的代码，从内存子系统检索的数据。

42. 发明申请

US20050152435A1 Encoded data 有权
标题翻译：编码数据
公开(公告)号：US20050152435A1
公开(公告)日：2005-07-14
申请号：US10756600
申请日：2004-01-12
申请人： Gregg Lesartre , Gary Gostin
发明人： Gregg Lesartre , Gary Gostin
IPC分类号： G06F13/42 , H04B1/69
CPC分类号： G06F13/4282 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L1/1635
摘要： A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.
摘要翻译：采用串行化器和解串器的数据通信架构可以减少数据通信延迟。在说明性实现中，数据通信架构通过通信链路传送数据。该架构维护各种机制，以提升数据通信速度，避免通信链路停机。这些机制执行的功能包括但不限于处理不确定的数据到达时间，检测单位和多位错误，处理通信链路故障，解决故障链路训练，识别和标记数据已损坏，以及识别和处理成功的数据事务通信链接。

43. 发明授权

US08724936B2 Optical polymorphic computer systems 有权
标题翻译：光学多态计算机系统
公开(公告)号：US08724936B2
公开(公告)日：2014-05-13
申请号：US12991638
申请日：2008-05-08
申请人： Gary Gostin , Michael Renne Ty Tan
发明人： Gary Gostin , Michael Renne Ty Tan
IPC分类号： G02B6/12 , G02B6/28 , H04B10/00
CPC分类号： H04B10/801
摘要： Embodiments of the present invention are directed to high-bandwidth, low-latency optical fabrics for broadcasting between nodes. In one embodiment, an optical fabric includes an optical communication path optically coupled to a broadcasting node and optically coupled to one or more broadcast receiving nodes. The optical fabric also includes a first optical element optically coupled to the optical communication path and configured to broadcast an optical signal generated by the broadcasting nodes onto the optical communication path, and one or more optical elements optically coupled to the optical communication path and configured to divert a portion the broadcast optical signal onto each of the one or more receiving nodes.
摘要翻译：本发明的实施例涉及用于在节点之间广播的高带宽，低延迟的光纤结构。在一个实施例中，光学结构包括光学耦合到广播节点并光学耦合到一个或多个广播接收节点的光通信路径。光学结构还包括光学耦合到光通信路径并被配置为将由广播节点产生的光信号广播到光通信路径上的第一光学元件以及光学耦合到光通信路径并被配置为将广播光信号的一部分转移到一个或多个接收节点中的每一个上。

44. 发明授权

US08705911B2 Bus-based scalable optical fabrics 有权
标题翻译：基于总线的可伸缩光学面料
公开(公告)号：US08705911B2
公开(公告)日：2014-04-22
申请号：US13258425
申请日：2009-05-06
申请人： Moray McLaren , Michael Renne Ty Tan , Gary Gostin
发明人： Moray McLaren , Michael Renne Ty Tan , Gary Gostin
IPC分类号： G02B6/28 , H04J14/00 , G02B6/293
CPC分类号： G02B6/2852 , G02B6/28 , G02B6/2938 , G02B6/29382 , G02B6/29383 , H04B10/801
摘要： Various embodiments of the present invention are directed to arrangements of multiple optical buses to create scalable optical interconnect fabrics for computer systems. In one aspect, a multi-bus fabric (102) for transmitting optical signals between a plurality of nodes (108-111) comprises a plurality of optical buses (104-107). Each optical bus is optically coupled to each node of the plurality of nodes, and each optical bus is configured to so that one node broadcasts optical signals generated by the node to the other nodes of the plurality of nodes.
摘要翻译：本发明的各种实施例涉及多个光学总线的布置，以便为计算机系统创建可伸缩的光学互连结构。一方面，用于在多个节点（108-111）之间传输光信号的多总线结构（102）包括多条光总线（104-107）。每个光总线被光耦合到多个节点中的每个节点，并且每个光总线被配置为使得一个节点将节点生成的光信号广播到多个节点中的其他节点。

45. 发明授权

US07437651B2 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US07437651B2
公开(公告)日：2008-10-14
申请号：US10879262
申请日：2004-06-29
申请人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1012
摘要： A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.
摘要翻译：一种用于控制在存储器子系统中应用纠错码（ECC）算法的擦除模式的方法包括使用ECC算法检测从存储器子系统检索的高速缓存行中的错误。该方法还分析错误以检测高速缓存行内的数据损坏的重复比特模式，将检测到的数据损坏的重复比特模式与存储器子系统的多个域之一相关联，并将ECC算法应用于擦除与从存储器子系统的相关域检索的来自高速缓存行的检测到的重复位模式。

46. 发明申请

US20080104293A1 Memory controller connection to RAM using buffer interface 有权
标题翻译：内存控制器使用缓冲区连接到RAM
公开(公告)号：US20080104293A1
公开(公告)日：2008-05-01
申请号：US11999834
申请日：2007-12-07
申请人： Theodore Briggs , John Westlick , Gary Gostin
发明人： Theodore Briggs , John Westlick , Gary Gostin
IPC分类号： G06F13/00
CPC分类号： G06F13/1673 , G06F12/0817
摘要： Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.
摘要翻译：提供了用于控制存储器控制器和连接到存储器的至少两个逻辑存储器总线之间的数据传输的存储器控制装置和方法，包括存储器控制器; 一个缓冲区连接控制器和缓冲器的双向数据总线; 连接控制器和缓冲器的控制接口，缓冲器连接至至少两个用于存储器读和写操作的逻辑存储器总线，该缓冲器包括用于在控制器和逻辑存储器总线之间缓冲数据的数据存储区域，以及逻辑电路从控制器解码存储器接口控制命令; 以及连接缓冲器和每个逻辑存储器总线的数据访问和控制总线，以控制存储器读和写操作。

47. 发明授权

US07308638B2 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US07308638B2
公开(公告)日：2007-12-11
申请号：US10879255
申请日：2004-06-29
申请人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在一个实施例中，计算机可读介质包括用于在从存储器子系统检索的数据中记录数据损坏的发生的代码，用于确定存储器子系统内的位位置是否与多次数据损坏相关联的代码，以及响应于用于确定的代码，包含与多次数据损坏相关联的位位置的存储器区域，用于分析在存储器子系统的多个地址上重复的数据损坏模式的代码，以及用于控制由所述存储器子系统的多个地址应用纠错码（ECC）算法的代码存储器子系统从从存储器子系统检索的数据中擦除与用于分析的代码检测的重复位模式相关联的位。

48. 发明申请

US20060064566A1 Communication in partitioned computer systems 失效
标题翻译：分区计算机系统中的通信
公开(公告)号：US20060064566A1
公开(公告)日：2006-03-23
申请号：US10947673
申请日：2004-09-23
申请人： Gary Gostin , Nathan Zelle
发明人： Gary Gostin , Nathan Zelle
IPC分类号： G06F12/00
CPC分类号： G06F12/0692 , G06F12/0284
摘要： One embodiment of a computer system has processors, having address spaces the processors can address directly. Each address space is directly linked to at least one other address space by memory within more than its own address space. The total size of the address spaces within the system linked together either directly or through directly linked address spaces is greater than the address space any resource within the system can address directly.
摘要翻译：计算机系统的一个实施例具有处理器，其具有处理器可直接寻址的地址空间。每个地址空间由多于其自己的地址空间内的存储器直接链接到至少一个其他地址空间。系统中直接或通过直接链接的地址空间链接在一起的系统中的地址空间的总大小大于系统中任何资源可以直接解决的地址空间。

49. 发明申请

US20050152386A1 Successful transactions 有权
标题翻译：成功交易
公开(公告)号：US20050152386A1
公开(公告)日：2005-07-14
申请号：US10756667
申请日：2004-01-12
申请人： Gregg Lesartre , Gary Gostin
发明人： Gregg Lesartre , Gary Gostin
IPC分类号： G06F12/06 , H04L1/00 , H04L1/18 , H04L12/54 , H04L29/06 , H04L29/08
CPC分类号： H04L1/1874 , H04L1/0061
摘要： A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.
摘要翻译：采用串行化器和解串器的数据通信架构可以减少数据通信延迟。在说明性实现中，数据通信架构通过通信链路传送数据。该架构维护各种机制，以提升数据通信速度，避免通信链路停机。这些机制执行的功能包括但不限于处理不确定的数据到达时间，检测单位和多位错误，处理通信链路故障，解决故障链路训练，识别和标记数据已损坏，以及识别和处理成功的数据事务通信链接。

50. 发明申请

US20150006977A1 SINGLE AND DOUBLE CHIP SPARE 有权
标题翻译：单和双芯片备件
公开(公告)号：US20150006977A1
公开(公告)日：2015-01-01
申请号：US14365191
申请日：2012-01-31
申请人： Gary Gostin , Erin A. Handgen
发明人： Gary Gostin , Erin A. Handgen
IPC分类号： G06F11/16 , G06F3/06
CPC分类号： G06F11/1666 , G06F3/0619 , G06F3/0658 , G06F3/0683 , G06F11/1064 , G06F11/1068 , G11C29/808
摘要： Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
摘要翻译：提供了克服内存故障的技术。存储器的一部分可以以单个芯片备用模式工作。当在存储器的该部分中检测到单个芯片中的错误时，存储器的该部分的区域可被转换为以双芯片备用模式工作。可以在单芯片和双芯片备用模式下访问存储器。

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