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    • 48. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08304856B2
    • 2012-11-06
    • US12880764
    • 2010-09-13
    • Keiji MitaYasuhiro TamadaMasao TakahashiTakao Maruyama
    • Keiji MitaYasuhiro TamadaMasao TakahashiTakao Maruyama
    • H01L27/02
    • H01L29/8611H01L27/0814
    • A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1. An N+ type buried layer and an N+ type conductive layer are formed to prevent an electric potential at the N+ type buried layer from becoming lower than an electric potential at a P+ type buried layer even when a large positive voltage is applied to the electrode AC1, so as to prevent a parasitic PNP transistor composed of the P+ type buried layer, the N+ type buried layer and the P type semiconductor substrate, that make an emitter, a base and a collector, respectively, from turning on.
    • 基于高耐压垂直PNP双极晶体管工艺技术,形成具有高耐受电压和低导通电阻的二极管串联二极管对。 两个二极管对并联连接形成桥,从而形成一个高效全波整流电路,该电路由于寄生晶体管而没有漏电流。 串联连接的二极管对通过连接由构成阳极的P型半导体衬底和形成阴极的N型掩埋层构成的二极管和由P +型导电层构成的二极管来形成, 阳极和N型外延层,其形成与电极AC1串联的阴极。 形成N +型掩埋层和N +型导电层,以防止N +型掩埋层的电位变得低于P +型掩埋层的电位,即使对电极AC1施加大的正电压, 以防止分别形成发射极,基极和集电极的由P +型掩埋层,N +型掩埋层和P型半导体基板构成的寄生PNP晶体管导通。
    • 49. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08232623B2
    • 2012-07-31
    • US12333418
    • 2008-12-12
    • Keiji MitaMasao TakahashiTakao Arai
    • Keiji MitaMasao TakahashiTakao Arai
    • H01L27/102
    • H01L29/7322H01L29/735H01L29/8618
    • A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.
    • 常规的半导体器件具有以下问题:当在饱和区域中使用作为功率半导体元件的垂直PNP晶体管时,产生进入衬底的漏电流。 在本发明的半导体器件中,以N型扩散层为基底形成作为集电极区域的2个P型扩散层。 P型扩散层中的一个形成为具有比其他P型扩散层更低的杂质浓度和更窄的扩散宽度。 在这种结构中,当垂直PNP晶体管导通时,形成前者P型扩散层的区域主要用作寄生电流路径。 因此,防止由衬底,N型掩埋层和P型掩埋层构成的寄生晶体管导通,并且防止了进入衬底的漏电流。