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41. 发明授权

US07356719B2 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US07356719B2
公开(公告)日：2008-04-08
申请号：US11357372
申请日：2006-02-21
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/26
CPC分类号： G06F1/04
摘要： In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with temperature. CPU reads out data stored in EEPROM in accordance with the temperature detected by a temperature detecting circuit, and sets the determined communication CMR into the communication circuit.
摘要翻译：在微型计算机的EEPROM中，存储数据，用于根据根据温度变化的CR振荡电路的振荡输出特性确定用于固定由通信电路管理的一帧的数据传输时间的通信速率CMR。 CPU根据温度检测电路检测到的温度读出存储在EEPROM中的数据，并将确定的通信CMR设置到通信电路中。

42. 发明授权

US07248092B2 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US07248092B2
公开(公告)日：2007-07-24
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

43. 发明授权

US07216250B2 Clock control circuit for correcting frequency of second clock signal based on first clock signal and monitoring oscillation state of first clock signal based on second clock signal 有权
标题翻译：时钟控制电路，用于基于第一时钟信号校正第二时钟信号的频率，并且基于第二时钟信号监视第一时钟信号的振荡状态
公开(公告)号：US07216250B2
公开(公告)日：2007-05-08
申请号：US10744645
申请日：2003-12-23
申请人： Toshihiko Matsuoka , Yoshinori Teshima , Shinichi Noda , Susumu Tsuruta , Hiroshi Fujii , Hideaki Ishihara
发明人： Toshihiko Matsuoka , Yoshinori Teshima , Shinichi Noda , Susumu Tsuruta , Hiroshi Fujii , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.
摘要翻译：时钟控制电路装置技术领域本发明涉及一种时钟控制电路装置，包括用于产生第一时钟信号的第一振荡电路和用于产生第二时钟信号的第二振荡电路，并且能够在使用两个时钟信号时提高可靠性振荡操作。在时钟控制电路装置中，子时钟校正单元基于主时钟信号校正子时钟信号的振荡频率，而主时钟监视单元基于主时钟信号监视主时钟信号的振荡状态的子时钟信号。

44. 发明申请

US20070083686A1 Communication system 失效
标题翻译：通讯系统
公开(公告)号：US20070083686A1
公开(公告)日：2007-04-12
申请号：US11519014
申请日：2006-09-12
申请人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Yoshinori Teshima , Hideaki Ishihara
发明人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F13/00
CPC分类号： H04L12/40045 , B60R2021/01047 , H04L12/403 , H04L2012/40273
摘要： A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.
摘要翻译：通信系统包括主控单元，多个从控单元和连接主控单元和用于异步通信的从控单元的总线。当主控制单元开始通信时，每个从控制单元基于通信的开始，发送由分配给从控制单元的数据传输期间总线是否被驱动到主控制单元所表示的多个数据位，并且主控制单元在数据传输期间驱动总线插入一个数据位发送期间供电。从控制单元在数据位传输周期结束时提供停止驱动总线的非驱动周期。

45. 发明申请

US20060195711A1 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US20060195711A1
公开(公告)日：2006-08-31
申请号：US11357372
申请日：2006-02-21
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/26
CPC分类号： G06F1/04
摘要： In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with temperature. CPU reads out data stored in EEPROM in accordance with the temperature detected by a temperature detecting circuit, and sets the determined communication CMR into the communication circuit.
摘要翻译：在微型计算机的EEPROM中，存储数据，用于根据根据温度变化的CR振荡电路的振荡输出特性确定用于固定由通信电路管理的一帧的数据传输时间的通信速率CMR。 CPU根据温度检测电路检测到的温度读出存储在EEPROM中的数据，并将确定的通信CMR设置到通信电路中。

46. 发明申请

US20060107082A1 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US20060107082A1
公开(公告)日：2006-05-18
申请号：US11270447
申请日：2005-11-10
申请人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
发明人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
IPC分类号： G06F1/30
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译：微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。多个操作模式选择端子被设计为可用作通用输入端子或输出端子。解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。

47. 发明授权

US06737905B1 Clamp circuit 失效
标题翻译：钳位电路
公开(公告)号：US06737905B1
公开(公告)日：2004-05-18
申请号：US10374695
申请日：2003-02-26
申请人： Shinichi Noda , Hideaki Ishihara , Akira Suzuki
发明人： Shinichi Noda , Hideaki Ishihara , Akira Suzuki
IPC分类号： H03K508
CPC分类号： H03K5/08 , G05F3/242
摘要： The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.
摘要翻译：钳位电路以在温度波动下稳定的规定的较高和较低钳位电压来钳位输入电压。晶体管Q12和Q14在它们的线性区域中导通。在较低电压钳位电路18中，Vin检测电路20通过电平移位Vin输出Va1，并通过串联电阻电路23对电平移位的Vin进行电压分压，而参考电压产生电路21通过电平移位输出Vr1 0 V由Q15和电压分压由串联电阻电路25的电平转换电压。当比较器22确定Va1下降并经过Vr1时，Q11接通。这里，Q12具有与Q14相同的特性，而Q13具有与Q15相同的特性。此外，电路23的电阻与电路25的电阻相同。较高电压钳位电路19类似于电路18。

48. 发明授权

US6054751A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US6054751A
公开(公告)日：2000-04-25
申请号：US932623
申请日：1997-09-17
申请人： Kouji Ichikawa , Hiroshi Fujii , Susumu Tsuruta , Hideaki Ishihara
发明人： Kouji Ichikawa , Hiroshi Fujii , Susumu Tsuruta , Hideaki Ishihara
IPC分类号： H01L21/02 , H01L21/768 , H01L27/06 , H01L29/00
CPC分类号： H01L28/40 , H01L21/768 , H01L27/0629
摘要： In an integrated circuit in which function blocks constituting a CPU block, a memory block and the like, a power supply line for supplying power to the function blocks, and multiple signal lines for inputting and outputting signals to and from the function blocks are formed on a semiconductor substrate, bypass capacitors are provided on the power supply line in proximity to or inside the function blocks. The capacitances of these bypass capacitors are set in correspondence with the consumed current characteristics of the respective function blocks. As a result, noise produced on the power supply line by the operation of the function blocks can be suppressed and it is possible to certainly prevent such noise from leaking out through power supply terminals and input/output terminals of the integrated circuit to the outside.
摘要翻译：在构成CPU块的功能块，存储块等的集成电路中，向功能块供电的电源线，以及用于向功能块输入和输出信号的多个信号线形成在半导体衬底，旁路电容器设置在功率块附近或内部的电源线上。这些旁路电容器的电容根据各功能块的消耗电流特性来设定。结果，可以抑制通过功能块的操作在电源线上产生的噪声，并且可以肯定地防止这种噪声通过集成电路的电源端子和输入/输出端子泄漏到外部。

49. 发明授权

US5790603A Communication apparatus with collision detection and edge detection for transmitting and receiving data 失效
标题翻译：具有碰撞检测和边缘检测的通信装置，用于发送和接收数据
公开(公告)号：US5790603A
公开(公告)日：1998-08-04
申请号：US546847
申请日：1995-10-23
申请人： Kouichi Maeda , Hideaki Ishihara , Tengo Fujii , Akihiro Sasaki , Yasushi Kanda
发明人： Kouichi Maeda , Hideaki Ishihara , Tengo Fujii , Akihiro Sasaki , Yasushi Kanda
IPC分类号： G06F13/00 , H04L12/413 , H04L7/00
CPC分类号： H04L12/40013 , H04L12/413
摘要： A communication apparatus is used in a communication system, having a communication line, where an operation timing in each of the communication apparatus is coupled to the communication line and synchronized with the received signals in each of the communication apparatus. This communication apparatus comprises a signal-chip microprocessor having a central processing unit for executing main and interruption processing, a register storing data to be transmitted next, an output buffer for transmitting the transmission data, and an edge detector for detecting an edge in the communication line. The output buffer is directly responsive to an edge detection circuit, so that the transmission data can be immediately transmitted in response to the detection of an edge without a variable delay time caused by the operation condition which may be varied by the interruption processing or like.
摘要翻译：在具有通信线路的通信系统中使用通信装置，其中通信装置中的每一个中的操作定时与通信线路耦合并且与每个通信装置中的接收信号同步。该通信装置包括：信号芯片微处理器，具有用于执行主处理和中断处理的中央处理单元，存储要接下来要发送的数据的寄存器，用于发送传输数据的输出缓冲器，以及用于检测通信中边缘的边缘检测器线。输出缓冲器直接响应于边缘检测电路，从而响应于边缘的检测而可以立即发送传输数据，而不会由可能由于中断处理等而改变的操作条件引起可变延迟时间。

50. 发明授权

US5737588A Driving circuit for a microcomputer that enables sleep control using a small-scale timer 失效
标题翻译：用于使用小型定时器进行睡眠控制的微型计算机的驱动电路
公开(公告)号：US5737588A
公开(公告)日：1998-04-07
申请号：US499174
申请日：1995-07-07
申请人： Kouichi Maeda , Hideaki Ishihara , Akihiro Sasaki
发明人： Kouichi Maeda , Hideaki Ishihara , Akihiro Sasaki
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , Y02B60/1221
摘要： For a system which receives a sleep command to terminate the application of machine clock signals to a microprocessor and which clocks control execution time and stabilization time after the return from sleep control and resumes the supply of the machine clock signal, the clocking device for each of the time durations is implemented using a small-scale timing device. Following a sleep command from a microprocessor, sleep control, which terminates the operation of the main oscillator and the machine clock generation circuit that generates the machine clock signal based on the oscillation of the main oscillator, is started. Then, counting the oscillation signal from an RC oscillator used for clocking using an RC timer, the lapse time after starting sleep control is started and if the clocked time reaches a predetermined time, the main oscillator is reactivated. After reactivating the main oscillator, the RC timer is reset so that it begins to count the time thereafter starting from "0" and if the clocked time reaches the time needed for the oscillation of the main oscillator to stabilize, the machine clock generation circuit resumes its operations.
摘要翻译：对于接收休眠命令以终止对微处理器的机器时钟信号的应用的系统，以及在从睡眠控制返回之后控制执行时间和稳定时间的时钟，并且恢复提供机器时钟信号的时钟控制装置，使用小规模定时装置实现持续时间。在从微处理器执行睡眠命令之后，开始基于主振荡器的振荡而终止主振荡器和产生机器时钟信号的机器时钟产生电路的操作的睡眠控制。然后，使用RC定时器对用于定时的RC振荡器进行振荡信号的计数，开始睡眠控制后的经过时间开始，如果时钟时间达到预定时间，则主振荡器被重新激活。在重新激活主振荡器之后，RC定时器复位，使其开始计数其后从“0”开始的时间，如果时钟时间达到主振荡器稳定所需的时间，则机器时钟产生电路恢复其业务。

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