专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20100219459A1 METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY, NON-VOLATILE MEMORY DEVICE, AND AN INTEGRATED CIRCUIT 有权
标题翻译：制造非易失性存储器，非易失性存储器件和集成电路的方法
公开(公告)号：US20100219459A1
公开(公告)日：2010-09-02
申请号：US12738409
申请日：2007-10-23
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.
摘要翻译：一种制造非易失性存储器件的方法，包括在衬底上提供至少一个控制栅极层。可以在至少一个控制栅极层和衬底之间产生通道。在通道中，可以提供至少一个填充层。可以形成包括填充层的浮动栅极结构，以及包括至少一个控制栅极层的控制栅极结构，所述控制栅极结构处于具有浮动栅极结构的层叠结构。

42. 发明授权

US07629220B2 Method for forming a semiconductor device and structure thereof 有权
标题翻译：半导体器件的形成方法及其结构
公开(公告)号：US07629220B2
公开(公告)日：2009-12-08
申请号：US11428038
申请日：2006-06-30
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/78684 , H01L29/66818 , H01L29/785
摘要： A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.
摘要翻译：非平面半导体器件（10）从硅片（42）开始。将锗源（例如24,26,28,30,32）提供给翅片（42）。一些实施例可以使用沉积来提供锗; 一些实施例可以使用离子注入（30）来提供锗; 也可以使用其它方法来提供锗。然后将翅片（42）氧化以在翅片（36）中形成硅锗通道区域。在一些实施例中，整个鳍（42）从硅转变为硅锗。可以使用一个或多个翅片（36）来形成非平面半导体器件，例如FINFET，MIGFET，三栅极晶体管或多栅极晶体管。

43. 发明申请

US20070218640A1 SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER 审中-公开
标题翻译：具有薄导电层的栅极的半导体器件
公开(公告)号：US20070218640A1
公开(公告)日：2007-09-20
申请号：US11752544
申请日：2007-05-23
申请人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
发明人： Sinan Goktepeli , Alexander Demkov , Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/42372
摘要： A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.
摘要翻译：描述了具有导电层薄的栅极的半导体器件。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用导电层的薄层，可以诱导导电层内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面的方向传播的模式。因此，可以减少器件中不期望的泄漏电流。附加的导电层可用于提供更多的载体。

44. 发明申请

US20070161170A1 Transistor with immersed contacts and methods of forming thereof 有权
标题翻译：具有浸入触点的晶体管及其形成方法
公开(公告)号：US20070161170A1
公开(公告)日：2007-07-12
申请号：US11311587
申请日：2005-12-16
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure of the semiconductor structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. The method further includes forming a first contact, wherein forming the first contact includes removing a first portion of the semiconductor structure to form an opening, wherein the opening is in the first current electrode region and forming contact material in the opening.
摘要翻译：一种包括形成半导体结构的方法，所述半导体结构包括第一电流电极区域，第二电流电极区域和沟道区域，所述沟道区域位于所述第一电流电极区域和所述第二电流电极区域之间，其中所述沟道区域位于半导体结构的翅片结构中，其中通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。所述方法还包括形成第一接触，其中形成所述第一接触包括移除所述半导体结构的第一部分以形成开口，其中所述开口位于所述第一电流电极区域中并在所述开口中形成接触材料。

45. 发明申请

US20070045735A1 FinFET structure with contacts 有权
标题翻译： FinFET结构与触点
公开(公告)号：US20070045735A1
公开(公告)日：2007-03-01
申请号：US11216974
申请日：2005-08-31
申请人： Marius Orlowski , Tab Stephens
发明人： Marius Orlowski , Tab Stephens
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/41733
摘要： A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain contacts away from the fins as much as reasonably possible. The gate contacts extend upward from the top surface of the elevated semiconductor portion. The gate also extends upward from the top surface of the elevated semiconductor portion. The contacts are located between the fins where the gate is below the height of the elevated semiconductor portion so the contacts are as far as reasonably possible from the gate, thereby reducing gate to drain capacitance and providing additional assistance to alignment tolerance.
摘要翻译： FinFET本质上具有升高的源极/漏极和升高的沟道，其是升高的半导体部分的部分，其在翅片的一侧具有平行的翅片和一个源极/漏极，另一个的另一个源极/漏极散热片，尽可能多地将所有的源极/漏极触点远离鳍片。栅极触点从升高的半导体部分的顶表面向上延伸。门也从升高的半导体部分的顶表面向上延伸。接触件位于翅片之间，其中栅极低于升高的半导体部分的高度，使得触点尽可能远离栅极，从而减小栅极到漏极电容，并为对准公差提供额外的辅助。

46. 发明申请

US20070001222A1 Single transistor memory cell with reduced recombination rates 失效
标题翻译：具有降低复合率的单晶体管存储单元
公开(公告)号：US20070001222A1
公开(公告)日：2007-01-04
申请号：US11172569
申请日：2005-06-30
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/7841 , H01L29/78687
摘要： A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
摘要翻译：半导体制造方法包括形成半导体结构，该半导体结构包括设置在沟道体两侧的源极/漏极区，其中源极/漏极区包括第一半导体材料，并且其中沟道主体包括第二半导体材料的迁移势垒。栅极电介质覆盖半导体结构，并且栅极模块覆盖在栅极电介质上。在第一和第二半导体材料之间的多数载流子势能级中的偏移对于通道体中的多数载流子产生潜在的井。迁移障碍物可以是第一半导体材料的第一层上的第二半导体材料层和第一半导体材料的覆盖层之下的层。在一维迁移屏障中，迁移屏障横向延伸穿过源极/漏极区域，而在二维屏障中，屏障在由栅极模块限定的边界处横向终止。

47. 发明申请

US20060286736A1 Method for forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060286736A1
公开(公告)日：2006-12-21
申请号：US11152931
申请日：2005-06-15
申请人： Marius Orlowski , Brian Goolsby
发明人： Marius Orlowski , Brian Goolsby
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823418
摘要： An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
摘要翻译：通过形成覆盖多个晶体管位置的第一和第二层来形成电子器件。执行蚀刻以去除第一层和第二层的部分以暴露多个晶体管位置的一部分，而第一层和第二层的其它部分保留以保护其他晶体管位置。随后，暴露的晶体管位置的源极/漏极位置与第二层的剩余部分一起被蚀刻。通过使用涉及第一层的端点检测技术去除第二层的部分来基本上终止蚀刻。随后在源极/漏极凹槽中形成外延层，以在晶体管位置的沟道区上提供应力。

48. 发明申请

US20060240629A1 Self correcting suppression of threshold voltage variation in fully depleted transistors 有权
标题翻译：完全耗尽晶体管中阈值电压变化的自校正抑制
公开(公告)号：US20060240629A1
公开(公告)日：2006-10-26
申请号：US11113589
申请日：2005-04-25
申请人： Marius Orlowski , Yasuhito Shiho
发明人： Marius Orlowski , Yasuhito Shiho
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/76283 , H01L29/78603
摘要： A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.
摘要翻译：半导体制造方法包括将反掺杂杂质分布注入或以其它方式引入到绝缘体上硅（SOI）晶片的半导体顶层中。顶层具有包括在第一区域处的第一厚度和大于第一区域的第二厚度的可变厚度。杂质分布被引入到顶层中，使得沉积在半导体顶层中的净电荷随着厚度变化而线性变化。反掺杂导致第一区域中的总净电荷近似等于第二区域中的净电荷。沉积的净电荷的这种变化导致用于完全耗尽的晶体管的均匀阈值电压。然后在顶层中形成完全耗尽的晶体管。

49. 发明申请

US20060068542A1 Isolation trench perimeter implant for threshold voltage control 有权
标题翻译：隔离沟槽周边植入用于阈值电压控制
公开(公告)号：US20060068542A1
公开(公告)日：2006-03-30
申请号：US10955658
申请日：2004-09-30
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.
摘要翻译：在半导体制造工艺中形成隔离沟槽以减少晶体管沟道边缘效应电流的方法包括形成覆盖衬底的掩模结构以暴露衬底的第一区域。隔板形成在掩蔽结构的侧壁上。间隔物覆盖第一区域的周边区域，从而留下暴露的第二较小区域。蚀刻第二区域下面的区域以形成隔离沟槽，然后填充电介质。去除间隔物以露出周边区域。使用掩模结构和沟槽电介质作为掩模，杂质分布被注入在周边区域下面的衬底的一部分中。因此，杂质分布围绕靠近衬底的上表面的沟槽电介质的周边。在典型情况下，周边杂质分布掺杂剂对于NMOS晶体管为p型，对于PMOS为n型。

50. 发明申请

US20060063392A1 Deposition and patterning of boron nitride nanotube ILD 有权
标题翻译：氮化硼纳米管的沉积和图案ILD
公开(公告)号：US20060063392A1
公开(公告)日：2006-03-23
申请号：US10945319
申请日：2004-09-20
申请人： Peter Ventzek , Kurt Junker , Marius Orlowski
发明人： Peter Ventzek , Kurt Junker , Marius Orlowski
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02112 , B82Y10/00 , H01L21/02282 , H01L21/318 , H01L21/76801 , H01L21/76813 , H01L21/76819 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.
摘要翻译：本文公开了形成电介质层的方法。根据该方法，提供第一材料（303），其包括纳米颗粒在液体介质中的悬浮液。然后通过蒸发过程从悬浮液在基底上形成介电层（305）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式