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41. 发明申请

US20050231563A1 Valve device, pressure regulator, carriage, liquid ejecting apparatus and method for manufacturing valve device 有权
标题翻译：阀装置，压力调节器，托架，液体喷射装置及阀装置的制造方法
公开(公告)号：US20050231563A1
公开(公告)日：2005-10-20
申请号：US11019665
申请日：2004-12-23
申请人： Takeshi Fujishiro , Osamu Takahashi
发明人： Takeshi Fujishiro , Osamu Takahashi
IPC分类号： B41J2/175 , B41J2/045
CPC分类号： F16K31/1266 , B41J2/17596 , G05D16/0647 , G05D16/0677 , Y10T137/783
摘要： A valve device has a pressure chamber, which is connected to a liquid inlet and a liquid outlet and retains liquid, and a pressure regulator decreasing the pressure in the pressure chamber to a predetermined level. The pressure regulator has a pressure receiving member. When the pressure in the pressure chamber becomes lower than the predetermined level, the pressure receiving member is elastically deformed in an inward direction of the pressure chamber. The pressure regulator generates actuation force greater than the pressing force produced by the elastic deformation of the pressure receiving member. The pressure regulator is configured to be opened by the actuation force. When the pressure regulator is open, a fluid supply from the liquid inlet to the pressure chamber is permitted. It is thus possible to minimize the valve device.
摘要翻译：阀装置具有连接到液体入口和液体出口并保持液体的压力室，以及将压力室中的压力降低到预定水平的压力调节器。压力调节器具有受压构件。当压力室中的压力变得低于预定水平时，受压构件在压力室的内部方向上弹性变形。压力调节器产生大于由受压构件的弹性变形产生的按压力的致动力。压力调节器构造成通过致动力打开。当压力调节器打开时，允许从液体入口到压力室的流体供应。因此可以使阀装置最小化。

42. 发明授权

US06944088B2 Apparatus and method for generating memory access signals, and memory accessed using said signals 失效
标题翻译：用于产生存储器访问信号的装置和方法，以及使用所述信号访问的存储器
公开(公告)号：US06944088B2
公开(公告)日：2005-09-13
申请号：US10262500
申请日：2002-09-30
申请人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F9/355 , G06F12/08 , G11C8/10 , G11C8/00
CPC分类号： G06F9/355 , G06F12/0895 , G11C8/10
摘要： A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals. Each of the selection signals activates a word line of the data array. A method is disclosed for producing signals for accessing a memory. Highest ordered portions of the first and second address signals are divided into multiple non-overlapping segments. An input signal (i.e., an I term) is generated for each of the segments, as is a carry signal. For each of the segments, when the corresponding carry signal is set, the corresponding I term is rotated one bit position. The I terms are produced as the signals.
摘要翻译：公开了一种和解解码器，其包括多个和预测解码器，进位发生器和多个旋转逻辑单元。每个和预解码器接收第一和第二地址信号的非重叠段的多个比特对，并且根据比特对产生输入信号。进位发生器接收第一和第二地址信号的低阶部分，并且产生每个对应于预测解码器中的不同一个的多个进位信号。每个旋转逻辑单元接收由相应的和预测码器和相应的一个进位信号产生的输入信号，根据进位信号旋转输入信号的位，并产生输入信号或旋转的输入信号作为输出信号。描述包括和解码器，最终解码块和数据阵列的存储器。最终解码块对和解码器的输出信号执行逻辑运算以产生选择信号。每个选择信号激活数据阵列的字线。公开了一种用于产生访问存储器的信号的方法。第一和第二地址信号的最高有序部分被分成多个非重叠段。对于每个段产生输入信号（即I项），进位信号也是如此。对于每个段，当相应的进位信号被设置时，对应的I项被旋转一位位置。我的条款是作为信号产生的。

43. 发明申请

US20050162708A1 Image reading apparatus 有权
标题翻译：图像读取装置
公开(公告)号：US20050162708A1
公开(公告)日：2005-07-28
申请号：US11041255
申请日：2005-01-25
申请人： Osamu Takahashi
发明人： Osamu Takahashi
IPC分类号： H04N1/19 , H04N1/393 , H04N1/40
CPC分类号： H04N1/40068
摘要： The image reading apparatus comprising an image sensor with plurality of reading devices one-dimensionally aligned in a main scanning direction allows reducing memory space necessary for image reduction process. Pixel signals in each channel read by a line image sensor are converted into pixel data in AFE, valid pixel data are captured therefrom, and then inputted into a reduction process unit. The reduction process unit skips pixel data sequentially inputted therein with predetermined intervals based on preset data reduction rate. Subsequently, pixel data after reduction process, that is only unskipped pixel data, are written into a memory via writing unit and memory control unit.
摘要翻译：包括具有在主扫描方向上一维排列的多个读取装置的图像传感器的图像读取装置允许减少图像缩小处理所需的存储空间。通过线图像传感器读取的每个通道中的像素信号被转换成AFE中的像素数据，从其中捕获有效像素数据，然后输入到缩小处理单元。缩小处理单元基于预设的数据缩小率，以预定间隔跳过依次输入的像素数据。随后，经过写入单元和存储器控制单元，将还原处理后的像素数据（即只有非贴片像素数据）写入存储器。

44. 发明授权

US06872059B2 Liquid discharger and apparatus including the liquid discharger 失效
标题翻译：排液器和包括排液器的装置
公开(公告)号：US06872059B2
公开(公告)日：2005-03-29
申请号：US10242547
申请日：2002-09-12
申请人： Osamu Takahashi , Masatoshi Moteki
发明人： Osamu Takahashi , Masatoshi Moteki
IPC分类号： F04C5/00 , F04B43/12 , F04B43/08
CPC分类号： F04B43/1269
摘要： A liquid discharger 1A has a base 2A where a resilient tube 100 is disposed in a tube guide groove 211A. A retainer 4A is rotatably provided at the base 2A, with a plurality of balls 5 being mounted at the retainer 4A so that the balls can roll. The cross sectional shape of a surface 211 defining the tube guide groove 211A that contacts the tube 100 has an arc shape formed concentrically with the balls 5. The balls 5, which are held by the retainer 4A, roll on the tube 100 while pressing and squashing a portion of the tube 100 as a rotor 3A rotates in order to discharge liquid inside the tube 100.
摘要翻译：排液器1A具有基部2A，其中弹性管100设置在管引导槽211A中。保持架4A可旋转地设置在基座2A处，多个球5安装在保持器4A上，使得球可以滚动。限定与管100接触的导向槽211A的表面211的横截面形状具有与滚珠5同心形成的弧形。由保持器4A保持的滚珠5在压制时在管100上滚动，当转子3A旋转时挤压管100的一部分以便排出管100内的液体。

45. 发明授权

US06717882B1 Cell circuit for multiport memory using 3-way multiplexer 失效
标题翻译：使用3路复用器的多端口存储器的单元电路
公开(公告)号：US06717882B1
公开(公告)日：2004-04-06
申请号：US10273590
申请日：2002-10-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.
摘要翻译：提供用于多端口存储器中的用于数据读出的改进的单元电路。多端口存储器存储写入数据信号。电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

46. 发明授权

US06600959B1 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays 失效
标题翻译：使用动态可编程逻辑阵列实现微处理器控制逻辑的方法和装置
公开(公告)号：US06600959B1
公开(公告)日：2003-07-29
申请号：US09498934
申请日：2000-02-04
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G05B1918
CPC分类号： H03K17/693 , H03K5/06
摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.
摘要翻译：在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

47. 发明授权

US06447193B1 Writing utensils 有权
标题翻译：书写用具
公开(公告)号：US06447193B1
公开(公告)日：2002-09-10
申请号：US09722424
申请日：2000-11-28
申请人： Hidehei Kageyama , Osamu Takahashi
发明人： Hidehei Kageyama , Osamu Takahashi
IPC分类号： B43K516
CPC分类号： B43K24/08
摘要： A writing utensil includes an external cylinder, a lead feeding mechanism housed in the external cylinder and propelling a lead forward, and a rear-end knocking member movable in conjunction with the lead feeding mechanism in an axial direction. The rear-end knocking member is integrally formed and includes a cylindrical section, a clip section, and a connecting section. The cylindrical section has a central hole into which the rear end of a lead case of the lead feeding mechanism is inserted and in which the rear of the cylindrical section protrudes from the rear end of the external cylinder. A clip section extends outside and along the external cylinder in an axial direction and a connecting section passing through a stem hole formed in the rear side face of the external cylinder for connecting the cylindrical section and the clip section together.
摘要翻译：书写用具包括：外筒，容纳在外筒中的引线供给机构，并且向前推进前端;以及后端敲击构件，其可与引线供给机构一起沿轴向移动。后端敲击构件一体形成并且包括圆柱形部分，夹子部分和连接部分。圆柱形部分具有中心孔，引线进给机构的引导壳体的后端插入其中，圆柱形部分的后部从外部圆筒的后端突出。夹子部分沿着轴向延伸到外部圆柱体外部，并且穿过形成在外部圆筒的后侧面中的杆孔的连接部分，用于将圆柱形部分和夹子部分连接在一起。

48. 发明授权

US06285218B1 Method and apparatus for implementing logic using mask-programmable dynamic logic gates 有权
标题翻译：使用掩码可编程动态逻辑门实现逻辑的方法和装置
公开(公告)号：US06285218B1
公开(公告)日：2001-09-04
申请号：US09567381
申请日：2000-05-10
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
IPC分类号： H03K19094
CPC分类号： H03K19/1736
摘要： A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.
摘要翻译：用于用可编程动态逻辑门实现动态逻辑的方法和装置作为用于高速微处理器设计中的可编程逻辑阵列（PLA）的补充。可选单元的矩阵提供强大的逻辑功能，例如具有最小输入和晶体管的AND-OR门能力。通过使用可编程逻辑阵列和可编程动态门，逻辑块的效率可以大大提高，几乎没有增加电路面积。

49. 发明授权

US06232798B1 Self-resetting circuit timing correction 失效
标题翻译：自复位电路定时校正
公开(公告)号：US06232798B1
公开(公告)日：2001-05-15
申请号：US09457938
申请日：1999-12-09
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K1900
CPC分类号： H03K19/0966
摘要： A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects an arrival of data from the input data path into the self-reset circuit and generates a normal-mode control signal in response thereto. The self-resetting circuit also includes a delay-mode input detect circuit for detecting the arrival of the data from the input data path and which generates a delay-mode control signal in response thereto. A toggle circuit is provided for disabling the normal-mode input detect circuit while simultaneously enabling the delay-mode input detect circuit. In response to the toggle circuit disabling the normal-mode input detect circuit, the delay-mode control signal propagates through a delay gate, such that said delay-mode control signal synchronizes said timing control path with respect to said data input path.
摘要翻译：一种具有用于使输入数据路径与定时控制路径同步的自复位电路的系统和方法。自复位电路包括正常模式输入检测电路，其检测数据从输入数据路径到达自复位电路，并响应于此产生正常模式控制信号。自复位电路还包括延迟模式输入检测电路，用于检测来自输入数据路径的数据的到达并响应于此生成延迟模式控制信号。提供了一种切换电路，用于在同时使能延迟模式输入检测电路的同时禁用正常模式输入检测电路。响应于切换电路禁用正常模式输入检测电路，延迟模式控制信号通过延迟门传播，使得所述延迟模式控制信号使所述定时控制路径相对于所述数据输入路径同步。

50. 发明授权

US5877972A High speed incrementer with array method 失效
标题翻译：具有阵列方法的高速增量器
公开(公告)号：US5877972A
公开(公告)日：1999-03-02
申请号：US783979
申请日：1997-01-15
申请人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
发明人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
IPC分类号： G06F7/38 , G06F7/50 , G06F7/505 , G06F7/508
CPC分类号： G06F7/5055
摘要： A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The input bit values are received as a plurality of complement input signals and a plurality of true input signals. The complement input signals are transmitted on the plurality of word lines that form the rows of the array. Each one of plurality of bit-line pairs is located in a respective column of the array and is coupled to particular ones of the word lines in the rows of the array. Each one of the plurality of sense amplifiers is coupled to a respective bit-line pair for sensing a voltage difference between the bit-line pair, such that the bit-line pair and the sense amplifier perform a logical NOR of the complement input signals to produce a NOR output. Each one of the plurality of exclusive-or gates is coupled to a respective NOR output and to a particular one of the true input signals for generating an incremented output signal.
摘要翻译：一种用于将数据输入值递增二进制数据的高速递增器阵列，其中数据输入值包括多个输入位值。增量器阵列包括多个字线，位线对和读出放大器。输入位值被接收为多个补码输入信号和多个真实输入信号。补码输入信号在形成阵列行的多条字线上传输。多个位线对中的每一个位于阵列的相应列中并且耦合到阵列的行中的特定字线。多个读出放大器中的每一个耦合到相应的位线对，用于感测位线对之间的电压差，使得位线对和读出放大器执行补码输入信号的逻辑或产生NOR输出。多个异或门中的每一个被耦合到相应的或非输出和真实输入信号中的特定一个以产生增加的输出信号。

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