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41. 发明申请

US20080151625A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ALLOWING EFFICIENT PROGRAMMING OPERATION AND ERASING OPERATION IN SHORT PERIOD OF TIME 审中-公开
标题翻译：非易失性半导体存储器件，能够在短时间内实现有效的编程操作和擦除操作
公开(公告)号：US20080151625A1
公开(公告)日：2008-06-26
申请号：US12020958
申请日：2008-01-28
申请人： Hidenori Mitani , Fumihiko Nitta , Tadaaki Yamauchi , Taku Ogura
发明人： Hidenori Mitani , Fumihiko Nitta , Tadaaki Yamauchi , Taku Ogura
IPC分类号： G11C16/04
CPC分类号： G11C29/84 , G11C16/10 , G11C16/16 , G11C16/22 , G11C16/30 , G11C16/344
摘要： Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.
摘要翻译：直到脉冲施加次数n达到12为止，作为前半脉冲，脉冲被设置为具有固定为2ms的宽度，并且其电压每次都增加。作为后半脉冲，脉冲被设置为具有固定为3ms的宽度，并且每次都增加脉冲电压直到达到最大电压。达到最大电压后，首先施加3 ms宽度的脉冲两次，施加最大电压的4 ms宽度的脉冲两次，最大电压为5 ms的脉冲宽度被应用两次。即使在达到最大电压之后，阈值电压的时间变化也可以更线性化。因此，可以提供允许在短时间段内进行有效的编程操作和擦除操作的非易失性半导体存储器件。

42. 发明申请

US20070120592A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070120592A1
公开(公告)日：2007-05-31
申请号：US11699427
申请日：2007-01-30
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

43. 发明申请

US20070097774A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20070097774A1
公开(公告)日：2007-05-03
申请号：US11639276
申请日：2006-12-15
申请人： Hidenori Mitani , Tadaaki Yamayuchi , Taku Ogura
发明人： Hidenori Mitani , Tadaaki Yamayuchi , Taku Ogura
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1006 , G11C11/56 , G11C2211/5641
摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.
摘要翻译：通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。高字数据LW和下字数据UW被分别压缩成8位的字节数据，并存储在存储单元阵列中。

44. 发明申请

US20050057995A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050057995A1
公开(公告)日：2005-03-17
申请号：US10936615
申请日：2004-09-09
申请人： Hidenori Mitani , Tadaaki Yamauchi , Taku Ogura
发明人： Hidenori Mitani , Tadaaki Yamauchi , Taku Ogura
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/08 , G11C7/00
CPC分类号： G11C8/10 , G11C7/1006 , G11C11/56 , G11C2211/5641
摘要： A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits; respectively, and stored in a memory cell array.
摘要翻译：通过利用用于存储2值数据的非易失性存储器件来实现用于存储具有三个或更多个值的多电平数据的多电平半导体存储器件。使用外部地址位AA [2]执行外部施加的连续16位数据的识别，并且使用外部地址位AA [23]选择存储块。高字数据LW和下字数据UW被压缩成8位的字节数据; 分别存储在存储单元阵列中。

45. 发明申请

US20050057963A1 Semiconductor memory device having memory block configuration 有权
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US20050057963A1
公开(公告)日：2005-03-17
申请号：US10940764
申请日：2004-09-15
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C16/06 , G11C5/02 , G11C8/08 , G11C11/00 , G11C16/02 , G11C16/16 , G11C16/26 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.
摘要翻译：包括存储器垫的存储器阵列在二维状态下被布置成U形，并且在由存储器阵列未占据的区域中布置逻辑电路和模拟电路。这有助于在包括模拟和逻辑电路的外围电路和包括电源和数据焊盘的焊盘带之间的电源电压和信号的传输。模拟电路位于靠近电源焊盘的位置，因此受限于电源互连电阻引起的电压降。还可以在电源板附近分离电荷泵浦电源互连和外围电路电源互连。

46. 发明授权

US06480057B2 Charge pump circuit allowing efficient electric charge transfer 有权
标题翻译：电荷泵电路允许有效的电荷转移
公开(公告)号：US06480057B2
公开(公告)日：2002-11-12
申请号：US09461004
申请日：1999-12-15
申请人： Taku Ogura
发明人： Taku Ogura
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/076
摘要： In a charge pump unit circuit, a P channel MOS transistor is connected between a gate and a drain of switching N channel MOS transistor. The P channel MOS transistor is controlled to be on/off by a switching circuit. A voltage doubling circuit generates a clock signal having amplitude twice that of power supply voltage. The clock signal is applied to a capacitor to increase the potential of the gate of the N channel MOS transistor. Thus, resistance of the N channel MOS transistor sufficiently is reduced and transfer efficiency of positive charge is enhanced.
摘要翻译：在电荷泵单元电路中，P沟道MOS晶体管连接在开关N沟道MOS晶体管的栅极和漏极之间。 P沟道MOS晶体管通过开关电路被控制为导通/截止。电压倍增电路产生幅度为电源电压的两倍的时钟信号。时钟信号被施加到电容器以增加N沟道MOS晶体管的栅极的电位。因此，N沟道MOS晶体管的电阻充分降低，正电荷的传输效率提高。

47. 发明授权

US06429724B1 Semiconductor device capable of generating a plurality of voltages 失效
标题翻译：能够产生多个电压的半导体器件
公开(公告)号：US06429724B1
公开(公告)日：2002-08-06
申请号：US09699370
申请日：2000-10-31
申请人： Taku Ogura , Masaaki Mihara
发明人： Taku Ogura , Masaaki Mihara
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/009 , H02M2003/071
摘要： Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.
摘要翻译：分别输出负电位（VN）和正电位（VPS）的输出节点（Noutn，Noutp）分别由未使用时由复位电路提供固定电位。当产生负电位时，开关（SW2，SW3）导通，而开关（SW1，SW4）在产生正电位时导通。所产生的电位的参考电位分别通过开关（SW1，SW3）提供给内部节点N10，N20）。多极二极管元件用于电压产生部分，由此可以实现能够产生正和负电压的电荷泵电路，而不显着地改变制造方法。

48. 发明授权

US6147547A Charge pump circuit capable of generating positive and negative voltages and nonvolatile semiconductor memory device comprising the same 有权
标题翻译：能够产生正负电压的电荷泵电路和包括该负电压的非易失性半导体存储器件
公开(公告)号：US6147547A
公开(公告)日：2000-11-14
申请号：US172769
申请日：1998-10-15
申请人： Taku Ogura , Masaaki Mihara
发明人： Taku Ogura , Masaaki Mihara
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073 , H02M2001/009 , H02M2003/071
摘要： Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes (N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.
摘要翻译：分别输出负电位（VN）和正电位（VPS）的输出节点（Noutn，Noutp）分别由未使用时由复位电路提供固定电位。当产生负电位时，开关（SW2，SW3）导通，而开关（SW1，SW4）在产生正电位时导通。所产生的电位的参考电位分别通过开关（SW1，SW3）提供给内部节点（N10，N20）。多极二极管元件用于电压产生部分，由此可以实现能够产生正和负电压的电荷泵电路，而不显着地改变制造方法。

49. 发明授权

US5991197A Semiconductor memory device having data protection feature 失效
标题翻译：具有数据保护功能的半导体存储器件
公开(公告)号：US5991197A
公开(公告)日：1999-11-23
申请号：US46583
申请日：1998-03-24
申请人： Taku Ogura , Atsushi Ohba , Tsuyoshi Honma , Kazuo Kobayashi
发明人： Taku Ogura , Atsushi Ohba , Tsuyoshi Honma , Kazuo Kobayashi
IPC分类号： G11C16/02 , G11C16/22 , G11C16/04
CPC分类号： G11C16/22
摘要： A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.
摘要翻译：复位停电模式指定信号和第一和第二写保护信号被提供给控制电路。根据这些外部控制信号的状态，为存储器阵列的每个存储块组设置无条件禁止，无条件许可和数据重写保护状态的锁定位（LB）依赖性的状态。因此，写保护状态可以灵活地设置为非易失性半导体存储器件。

50. 发明申请

US20120230107A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION 失效
标题翻译：具有存储块配置的半导体存储器件
公开(公告)号：US20120230107A1
公开(公告)日：2012-09-13
申请号：US13481540
申请日：2012-05-25
申请人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
发明人： Taku Ogura , Tadaaki Yamauchi , Hidenori Mitani , Takashi Kubo , Kengo Aritomi
IPC分类号： G11C16/04
CPC分类号： G11C29/50 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C29/80 , G11C29/82 , G11C29/832 , G11C2029/1202 , G11C2029/4402 , G11C2029/5006
摘要： A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.
摘要翻译：半导体器件包括具有第一和第二边缘线的半导体衬底，沿着第一边缘线的地址焊盘和存储器衬垫，每个存储器衬垫都包括正常存储器块和备用存储块。每个正常的存储器块都具有非易失性存储器单元，并且是批量擦除的单元。存储垫被布置在具有面向第二边缘线的中空部分的U形区域中。该设备包括对应于存储器垫布置的列解码器，布置在中空部分中的模拟/逻辑电路以及布置在模拟/逻辑电路和第二边缘线之间的电源焊盘。模拟/逻辑电路包括电荷泵电路。该设备还包括从电源焊盘向电荷泵电路供应电源电压的第一电源互连和从电源焊盘向列解码器供电电源电压的第二电源互连。

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