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41. 发明申请

US20060094135A1 Method of making semiconductor devices 失效
公开(公告)号：US20060094135A1
公开(公告)日：2006-05-04
申请号：US11300481
申请日：2005-12-15
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/66
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

42. 发明申请

US20060040479A1 Method of making semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060040479A1
公开(公告)日：2006-02-23
申请号：US11018242
申请日：2004-12-22
申请人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
发明人： Cha-Hsin Lin , Zing-Way Pei , Shing-Chii Lu , Wen-Yi Hsieh
IPC分类号： H01L21/04
CPC分类号： H01L21/823807 , H01L21/31155 , H01L29/7843
摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.
摘要翻译：提供一种制造半导体器件的方法。在半导体器件的晶体管的两面上形成的高应力层用作盖层。然后通过光电阻掩模限定特定区域，并且通过离子注入改变该区域的应力。因此，在高应力层上产生压缩应力和拉伸应力。根据所公开的方法，高应力层可以同时改善在同一晶片上形成的晶体管的特性。此外，装置的载体的移动性增强。

43. 发明授权

US06316323B1 Method for forming bridge free silicide by reverse spacer 失效
标题翻译：通过反向间隔物形成无桥硅化物的方法
公开(公告)号：US06316323B1
公开(公告)日：2001-11-13
申请号：US09532847
申请日：2000-03-21
申请人： Edberg Fang , Wen-Yi Hsieh , Teng-Chun Tsai
发明人： Edberg Fang , Wen-Yi Hsieh , Teng-Chun Tsai
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/66492 , H01L29/665 , H01L29/66537 , H01L29/66553
摘要： The proposed invention is used to prevent the bridging issue of salicide process and also to provide a self-aligned contacted process in conventional self-aligned silicide process. In short, the proposed invention is a two-step silicide process with a reverse spacer structure, and comprises following steps: providing a substrate; forming a pad layer on the substrate; forming a first cap layer on the pad layer; defining a trench region over the substrate and forming the trench; implanting first ions into part of the substrate that is uncovered by the first layer; forming a pair of spacers inside the trench; implanting second ions into part of the substrate that is not covered by the first layer and the spacers; forming a gate oxide layer that is located inside the trench; filling a polysilicon layer into the trench; capping a first metal layer on the polysilicon layer; performing a first rapid thermal process; removing unreacted the first metal layer; filling the trench by a second cap layer; removing the first cap layer and the pad layer that are not located inside the trench region, and then a gate structure is formed; forming a source and a drain inside the substrate; forming a second metal layer on the substrate; performing a second rapid thermal process; removing unreacted the second metal layer; performing a third rapid thermal process; forming a third cap layer on the substrate; and forming a pair of contacts inside the third cap layer.
摘要翻译：所提出的发明用于防止自对准硅化物工艺的桥接问题，并且还提供了常规自对准硅化物工艺中的自对准接触工艺。简而言之，本发明是具有反向间隔结构的两步硅化物工艺，包括以下步骤：提供衬底; 在衬底上形成衬垫层; 在所述垫层上形成第一盖层; 在衬底上限定沟槽区域并形成沟槽; 将第一离子注入未被第一层覆盖的部分基底; 在沟槽内形成一对垫片; 将第二离子注入未被第一层和间隔物覆盖的基底的一部分中; 形成位于沟槽内的栅氧化层; 将多晶硅层填充到沟槽中; 在多晶硅层上覆盖第一金属层; 执行第一快速热处理; 去除未反应的第一金属层; 通过第二盖层填充沟槽; 去除不位于沟槽区域内的第一覆盖层和焊盘层，然后形成栅极结构; 在衬底内形成源极和漏极; 在所述基板上形成第二金属层; 执行第二快速热处理; 去除未反应的第二金属层; 进行第三次快速热处理; 在所述基板上形成第三盖层; 以及在所述第三盖层内形成一对触点。

44. 发明授权

US06228709B1 Method of fabricating hemispherical grain electrode 失效
标题翻译：制造半球形晶粒电极的方法
公开(公告)号：US06228709B1
公开(公告)日：2001-05-08
申请号：US09010684
申请日：1998-01-22
申请人： Wen-Yi Hsieh
发明人： Wen-Yi Hsieh
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/31111 , H01L27/1085
摘要： A method of fabricating an HSG electrode. An electrode is defined before the formation of an HSG layer. The HSG layer is then formed on the top surface and the side wall of the electrode. The HSG layer is thermal oxidized in a furnace by rapid thermal process, and a silicon oxide layer is formed on the surface of the HSG layer. Dipping the electrode into a dilute solution of hydrogen fluoride or buffered oxide etching (BOE), the silicon oxide layer is lifted off while an HSG structure is remained on the top surface and the side wall of the electrode.
摘要翻译：一种HSG电极的制造方法。在形成HSG层之前定义电极。然后在电极的顶表面和侧壁上形成HSG层。 HSG层通过快速热处理在炉中进行热氧化，并且在HSG层的表面上形成氧化硅层。将电极浸入氟化氢或缓冲氧化物蚀刻（BOE）的稀释溶液中，氧化硅层被剥离，同时HSG结构保留在电极的顶表面和侧壁上。

45. 发明授权

US6022795A Salicide formation process 失效
公开(公告)号：US6022795A
公开(公告)日：2000-02-08
申请号：US73861
申请日：1998-05-07
申请人： Tung-Po Chen , Hong-Tsz Pan , Wen-Yi Hsieh
发明人： Tung-Po Chen , Hong-Tsz Pan , Wen-Yi Hsieh
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

46. 发明授权

US08926194B2 Optical board having separated light circuit holding member and optical layer 有权
标题翻译：具有分离的光电路保持构件和光学层的光学板
公开(公告)号：US08926194B2
公开(公告)日：2015-01-06
申请号：US13014794
申请日：2011-01-27
申请人： Yen-Chih Chang , Wen-Yi Hsieh , Ke-Hao Chen
发明人： Yen-Chih Chang , Wen-Yi Hsieh , Ke-Hao Chen
IPC分类号： G02B6/36
CPC分类号： G02B6/36
摘要： An optical board (100) includes a base layer (1), an optical module (4) assembled to the base layer, and an optical layer (2) attached to the base layer and defining a receiving recess (23). The optical module includes a ferrule (41) received in the receiving recess and defining a number of grooves (4131), and a number of optical circuits (42) positioned in the grooves of the ferrule. The optical circuits extend outside of the ferrule and into the optical layer.
摘要翻译：光学板（100）包括基底层（1），组装到基底层的光学模块（4）和安装在基底层上并限定接纳凹部（23）的光学层（2）。光学模块包括容纳在容纳凹槽中并限定多个凹槽（4131）的套圈（41）和位于套圈凹槽中的多个光学电路（42）。光学电路延伸到套圈的外部并进入光学层。

47. 发明授权

US08174904B2 Memory array and method of operating one of a plurality of memory cells 有权
标题翻译：存储器阵列和操作多个存储器单元之一的方法
公开(公告)号：US08174904B2
公开(公告)日：2012-05-08
申请号：US12898691
申请日：2010-10-05
申请人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
发明人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/04 , G11C16/3445 , G11C29/50 , G11C29/50004 , G11C29/52
摘要： An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.
摘要翻译：本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。

48. 发明授权

US07963778B2 Burn-in socket with plated contacts 有权
标题翻译：带电镀触点的老化插座
公开(公告)号：US07963778B2
公开(公告)日：2011-06-21
申请号：US12317651
申请日：2008-12-23
申请人： Ming-Yue Chen , Been-Yang Liaw , Wen-Yi Hsieh , Shih-Wei Hsiao
发明人： Ming-Yue Chen , Been-Yang Liaw , Wen-Yi Hsieh , Shih-Wei Hsiao
IPC分类号： H01R12/00
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2863 , H01R12/585 , H01R12/89 , H01R13/03 , H01R13/11 , H01R2201/20
摘要： A burn-in socket for receiving an IC package comprises a socket body, a plurality of contacts mounted in the socket body and an actuator movably mounted upon the socket body. Each contact in the socket body includes a pair of clipping arms with tip portions at free ends thereof respectively. Solder balls attached to the bottom of the IC package are respectively clipped between the pair of the tip portions and thus the IC package should be brought into electrical contact with the contacts of the burn-in socket. The tip portion is plated with a Pd—Co layer for reducing the attachment of the Sn and preventing the impedance of the contacts to increase. Meanwhile, the IC package can be sucked up successfully without absorption from the contacts of the burn-in socket.
摘要翻译：用于接收IC封装的老化插座包括插座主体，安装在插座主体中的多个触点和可移动地安装在插座主体上的致动器。插座主体中的每个触点分别具有一对夹持臂，其顶端部分分别在其自由端。附着在IC封装的底部的焊球分别夹在一对尖端部分之间，因此IC封装应与老化插座的触点电接触。尖端部分镀有Pd-Co层，以减少Sn的附着并防止触点的阻抗增加。同时，IC封装可以成功吸入，而不会从老化插座的触点吸收。

49. 发明授权

US07956631B2 Test socket for testing semiconductor package 有权
公开(公告)号：US07956631B2
公开(公告)日：2011-06-07
申请号：US12381420
申请日：2009-03-10
申请人： Ke-Hao Chen , Wen-Yi Hsieh
发明人： Ke-Hao Chen , Wen-Yi Hsieh
IPC分类号： G01R31/00
CPC分类号： G01R1/0466 , G01R1/07357
摘要： A test socket, adapted for connecting the semiconductor package and a printed circuit board comprises a base and a plurality of contacts received in the base. The base has a retaining board defining a plurality of first receiving holes and a positioning board defining a plurality of second receiving holes. The contacts has a contacting portion, an elastic portion and a retaining portion, the elastic portion is disposed between the retaining board and the positioning board and protruding rightward, and the contacting portion extends beyond the elastic portion and defines a acute angle with a horizontal line in a right hand before contacting with the semiconductor package to prevent the contacting portion from scratching with the left inner sidewall of the second receiving hole when pushed downward by the semiconductor package and rotating leftward.

50. 发明申请

US20080299810A1 Burn-in-socket having slider arrangments 失效
标题翻译：插入式插座具有滑块排列
公开(公告)号：US20080299810A1
公开(公告)日：2008-12-04
申请号：US12156288
申请日：2008-05-30
申请人： Wen-Yi Hsieh , Ke-Hao Chen
发明人： Wen-Yi Hsieh , Ke-Hao Chen
IPC分类号： H01R4/50
CPC分类号： G01R1/0466 , G01R31/2863
摘要： A burn-in socket for receiving an IC package includes a base, a platform located within the base for loading the IC package, a number of contacts arranged in the base for connecting with the IC package, a cover movably mounted upon the base, and at least one slider arrangement actuated by the cover. The slider arrangement comprises a first rod pivotally connected to the cover, a slider capable of abutting against the IC package, and a second rod with one end pivotally connected to the first rod and the other end pivotally connected to the slider.
摘要翻译：用于接收IC封装的老化插座包括基座，位于基座内用于装载IC封装的平台，布置在基座中的与IC封装连接的多个触点，可移动地安装在基座上的盖子，以及由盖驱动的至少一个滑动装置。滑动装置包括一个可枢转地连接到该盖的第一杆，一个能够抵靠IC封装的滑块和一个第二杆，其一端可枢转地连接到第一杆，而另一端枢转地连接到滑块。

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