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41. 发明授权

US07406585B2 Data processing system having an external instruction set and an internal instruction set 失效
标题翻译：数据处理系统具有外部指令集和内部指令集
公开(公告)号：US07406585B2
公开(公告)日：2008-07-29
申请号：US10609538
申请日：2003-07-01
申请人： Andrew Christopher Rose , Krisztian Flautner
发明人： Andrew Christopher Rose , Krisztian Flautner
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3836 , G06F9/3844 , G06F9/3861
摘要： There is provided a system havingan execution core operable to execute internal instructions.A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions.A remapper is responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer. Thus one or more internal instructions from said corresponding internal instruction block can be supplied to execution core.
摘要翻译：提供了一种具有可执行内部指令的执行核心的系统。翻译缓冲器可操作以存储一个或多个内部指令的多个内部指令块，其中内部指令块是一个或多个外部指令的相应外部指令块的动态转换。再映射器响应于在所述外部指令块之一内的外部指令的执行请求，以识别存储在所述转换缓冲器内的对应的内部指令块。因此，可以将来自所述对应的内部指令块的一个或多个内部指令提供给执行核心。

42. 发明授权

US07350055B2 Tightly coupled accelerator 有权
标题翻译：紧耦合加速器
公开(公告)号：US07350055B2
公开(公告)日：2008-03-25
申请号：US11046555
申请日：2005-01-31
申请人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F8/44 , G06F9/3005 , G06F9/30054 , G06F9/3806 , G06F9/3836 , G06F9/3897
摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
摘要翻译：加速器120紧密耦合到正常执行单元110。执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。操作数也可以在指令本身内作为立即值访问。与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。本技术规定，在加速器内产生但被确定为不被引用在有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

43. 发明申请

US20070266385A1 Performance level setting in a data processing system 审中-公开
标题翻译：数据处理系统中的性能级别设置
公开(公告)号：US20070266385A1
公开(公告)日：2007-11-15
申请号：US11431928
申请日：2006-05-11
申请人： Krisztian Flautner , Catalin Marinas
发明人： Krisztian Flautner , Catalin Marinas
IPC分类号： G06F9/46
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance range of a processor in a data processing apparatus is dynamically varied by recalculating at least one performance-range limit in dependence upon a quality of service value for a give processing task. The processor performance level is varied by selecting from a plurality of possible performance levels of a performance range having the performance-range limit.
摘要翻译：通过根据给出处理任务的服务质量值重新计算至少一个性能范围限制来动态地改变数据处理装置中处理器的性能范围。通过从具有性能范围限制的性能范围的多个可能的性能水平中进行选择来改变处理器性能水平。

44. 发明授权

US07260694B2 Data processor memory circuit 有权
标题翻译：数据处理器存储电路
公开(公告)号：US07260694B2
公开(公告)日：2007-08-21
申请号：US11526687
申请日：2006-09-26
申请人： Krisztian Flautner , Trevor N. Mudge
发明人： Krisztian Flautner , Trevor N. Mudge
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.
摘要翻译：描述了一种在数据处理电路中使用的存储器电路，其中存储单元具有至少两个状态，每个状态由对应于第一电源线的第一电压电平和对应于第二电源线的第二电压电平确定。存储电路包括可读状态，其中存储在存储单元中的信息是可读的，并且存储在所述存储单元中的信息被可靠地保留但不可读的不可读状态。改变第一电压电平但保持第二电压电平基本上恒定会影响可读状态和不可读状态之间的转换。在使用中，处于不可读状态的存储单元的静态功耗小于可读状态下的存储单元的静态功耗。

45. 发明授权

US07055007B2 Data processor memory circuit 有权
公开(公告)号：US07055007B2
公开(公告)日：2006-05-30
申请号：US10410602
申请日：2003-04-10
申请人： Krisztian Flautner , David T. Blaauw , Trevor N. Mudge , Nam S. Kim , Steven M. Martin
发明人： Krisztian Flautner , David T. Blaauw , Trevor N. Mudge , Nam S. Kim , Steven M. Martin
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

46. 发明申请

US20060095721A1 Tightly coupled accelerator 有权
标题翻译：紧耦合加速器
公开(公告)号：US20060095721A1
公开(公告)日：2006-05-04
申请号：US11046555
申请日：2005-01-31
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F8/44 , G06F9/3005 , G06F9/30054 , G06F9/3806 , G06F9/3836 , G06F9/3897
摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
摘要翻译：加速器120紧密耦合到正常执行单元110。执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。操作数也可以在指令本身内作为立即值访问。与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。本技术提供了在加速器内生成但被确定不被引用到有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

47. 发明申请

US20060095720A1 Reuseable configuration data 有权
标题翻译：可重复使用的配置数据
公开(公告)号：US20060095720A1
公开(公告)日：2006-05-04
申请号：US11044734
申请日：2005-01-28
申请人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F8/433 , G06F8/44 , G06F9/30043 , G06F9/3005 , G06F9/30054 , G06F9/3017 , G06F9/30174 , G06F9/3806 , G06F9/3897
摘要： There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units, said accelerator being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation; wherein said accelerator executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.
摘要翻译：提供了一种用于执行程序的信息处理器，该程序包括多个单独的程序指令：可操作以单独执行所述程序的所述单独的程序指令的处理逻辑; 可操作地存储操作数值的操作数存储器; 以及具有包括多个功能单元的阵列的加速器，所述加速器可操作以通过配置所述多个功能单元中的各个功能单元执行与一个功能单元相关联的特定处理操作来执行对应于所述单独程序指令的计算子图的组合操作或更多的处理阶段; 其中所述加速器根据操作数映射数据执行所述组合操作，所述操作数映射数据提供所述组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供所述多个功能单元之间的映射和所述特定处理使得所述配置数据可以被重新用于不同的操作数映射的操作。

48. 发明申请

US20060074576A1 Operating voltage determination for an integrated circuit 有权
公开(公告)号：US20060074576A1
公开(公告)日：2006-04-06
申请号：US11294431
申请日：2005-12-06
申请人： Dipesh Patel , Krisztian Flautner
发明人： Dipesh Patel , Krisztian Flautner
IPC分类号： G01R19/00
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

49. 发明授权

US07533226B2 Data processor memory circuit 有权
标题翻译：数据处理器存储电路
公开(公告)号：US07533226B2
公开(公告)日：2009-05-12
申请号：US11353024
申请日：2006-02-14
申请人： Krisztian Flautner , David T. Blaauw , Trevor N. Mudge , Nam S. Kim , Steven M. Martin
发明人： Krisztian Flautner , David T. Blaauw , Trevor N. Mudge , Nam S. Kim , Steven M. Martin
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.
摘要翻译：描述了一种在数据处理电路中使用的存储器电路，其中存储单元具有至少两个状态，每个状态由对应于第一电源线的第一电压电平和对应于第二电源线的第二电压电平确定。存储电路包括可读状态，其中存储在存储单元中的信息是可读的，并且存储在所述存储单元中的信息被可靠地保留但不可读的不可读状态。改变第一电压电平但保持第二电压电平基本上恒定会影响可读状态和不可读状态之间的转换。在使用中，处于不可读状态的存储单元的静态功耗小于可读状态下的存储单元的静态功耗。

50. 发明申请

US20080263332A1 Data Processing Apparatus and Method for Accelerating Execution Subgraphs 有权
标题翻译：用于加速执行子图的数据处理装置和方法
公开(公告)号：US20080263332A1
公开(公告)日：2008-10-23
申请号：US11884362
申请日：2005-06-22
申请人： Sami Yehia , Krisztian Flautner
发明人： Sami Yehia , Krisztian Flautner
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3877
摘要： A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs.
摘要翻译：提供了一种数据处理装置和方法，用于在具有程序指令的程序的控制下处理数据，该程序指令包括与程序内识别的计算子图相对应的各个程序指令的序列。每个计算子图具有多个输入操作数，并产生一个或多个输出操作数。该装置包括用于存储输入和输出操作数的操作数存储器和用于从程序执行各个程序指令的处理逻辑。还提供了可配置加速器逻辑，其响应于到达程序内的执行点，对应于与计算子图对应的单独程序指令的序列，来评估与计算子图相关联的一个或多个输出函数。每个输出函数的评估产生用于存储在操作数存储中的输出操作数，并且每个输出操作数对应于如果已经由处理逻辑执行了与计算子图对应的各个程序指令的序列，则该输出将被产生。配置存储器存储用于每个输出功能的单个查找表（LUT）配置，并且对于要评估的每个输出功能，加速器逻辑被配置为取决于来自配置存储器的相关联的单个LUT配置，使得在接收到输入操作数的计算子图，加速器逻辑将产生输出操作数。已经发现这种技术提供了用于评估与计算子图相关联的输出函数的特别有效的加速器逻辑。

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