会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 43. 发明授权
    • Electron beam pattern line width measurement system
    • 电子束图案线宽测量系统
    • US4740693A
    • 1988-04-26
    • US807681
    • 1985-12-11
    • Yoshinori NakayamaShinji OkazakiHidehito ObayashiMikio Ichihashi
    • Yoshinori NakayamaShinji OkazakiHidehito ObayashiMikio Ichihashi
    • G01S13/74G01B7/02G01B15/00H01J37/28G01B7/14
    • H01J37/28G01B15/00G01B7/02
    • Disclosed is an electron beam pattern line width measurement system wherein an electron beam is converged to a fine spot, the electron beam is scanned on a sample formed with a pattern to-be-measured, secondary electrons generated from a surface of the sample by the projection of the electron beam are detected, and the detected signal is processed to determine a line width of the pattern to-be-measured, comprising a secondary electron detector which detects a signal corresponding to an amount of all secondary electrons generated by the scanning, and a secondary electron energy analyzer which selectively detects a signal corresponding to an amount of secondary electrons of specified energy. With the electron beam pattern line width measurement system, it becomes possible to precisely detect a pattern boundary region defined by different sorts of materials in a stepped structure of a small level difference not having been measurable with a prior-art electron beam pattern line width measurement system.
    • 公开了一种电子束图案线宽度测量系统,其中电子束会聚到细微点,电子束在形成有要测量图案的样品上扫描,从样品表面产生的二次电子被 检测电子束的投影,并且处理检测信号以确定要测量的图案的线宽,包括二次电子检测器,其检测对应于由扫描产生的所有二次电子的量的信号, 以及二次电子能量分析器,其选择性地检测与特定能量的二次电子量对应的信号。 利用电子束图案线宽度测量系统,可以精确地检测由现有技术的电子束图案线宽度测量不能测量的小电平差的阶梯式结构中由不同种类的材料限定的图案边界区域 系统。
    • 47. 发明申请
    • Defect inspection method and its system
    • 缺陷检查方法及其系统
    • US20090206252A1
    • 2009-08-20
    • US12320574
    • 2009-01-29
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • G01N23/00
    • H01L22/12G06T7/0006G06T7/001G06T2207/10056G06T2207/30148H01L2924/0002H01L2924/00
    • A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
    • 一种能够容易地管理半导体集成图案的致命缺陷的方法,该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据,以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据 分别。 该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷,同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上,并将这些缺陷存储为热点信息。 此外,该方法还能够将设计意图数据与热点信息组合,以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点,并显着缩短缺陷检查时间。