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41. 发明申请

US20090213670A1 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 有权
标题翻译：非同步性，使用校准时序元素的高带宽存储器组件
公开(公告)号：US20090213670A1
公开(公告)日：2009-08-27
申请号：US12434989
申请日：2009-05-04
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

42. 发明申请

US20080144408A1 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 失效
标题翻译：非同步性，使用校准时序元素的高带宽存储器组件
公开(公告)号：US20080144408A1
公开(公告)日：2008-06-19
申请号：US12041594
申请日：2008-03-03
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

43. 发明授权

US07362626B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 有权
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US07362626B2
公开(公告)日：2008-04-22
申请号：US11165797
申请日：2005-06-24
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

44. 发明授权

US07148699B1 Technique for calibrating electronic devices 失效
标题翻译：校准电子设备的技术
公开(公告)号：US07148699B1
公开(公告)日：2006-12-12
申请号：US10298541
申请日：2002-11-19
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G01R35/00
CPC分类号： G11C7/1048 , G01R35/00 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2207/2254
摘要： A technique for calibrating a second electronic device using a first electronic device having a reference characteristic is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for calibrating a second electronic device using a first electronic device, wherein the first electronic device has a reference characteristic, wherein the second electronic device has an adjustable element, and wherein the first electronic device and the second electronic device are interconnected via one or more signal lines. The method comprises generating a first value based at least in part upon the reference characteristic, and providing the first value to the second electronic device via one of the one or more signal lines. The method also comprises generating a second value, based at least in part upon the first value, using the adjustable element. The method further comprises comparing the second value to the first value, and adjusting the adjustable element so as to modify the second value until the second value substantially matches the first value.
摘要翻译：公开了一种使用具有参考特性的第一电子设备校准第二电子设备的技术。在一个特定的示例性实施例中，该技术可以被实现为用于使用第一电子设备校准第二电子设备的方法，其中第一电子设备具有参考特性，其中第二电子设备具有可调节元件，并且其中第一电子设备电子设备和第二电子设备经由一个或多个信号线互连。所述方法包括至少部分地基于所述参考特征产生第一值，以及经由所述一个或多个信号线之一将所述第一值提供给所述第二电子设备。该方法还包括使用可调节元件至少部分地基于第一值产生第二值。所述方法还包括将所述第二值与所述第一值进行比较，以及调整所述可调整元件以便修改所述第二值直到所述第二值基本上与所述第一值匹配。

45. 发明授权

US06990042B2 Single-clock, strobeless signaling system 失效
公开(公告)号：US06990042B2
公开(公告)日：2006-01-24
申请号：US11053884
申请日：2005-02-10
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.

46. 发明授权

US06889304B2 Memory device supporting a dynamically configurable core organization 有权
公开(公告)号：US06889304B2
公开(公告)日：2005-05-03
申请号：US10302420
申请日：2002-11-22
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware
IPC分类号： G06F12/04 , G06F12/06 , G11C5/00 , G11C5/04 , G11C7/10 , G11C8/00 , G11C11/408 , G11C11/4097 , H05K1/11 , H05K1/14 , G06F12/00 , G06F12/02
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

47. 发明授权

US06788594B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
公开(公告)号：US06788594B2
公开(公告)日：2004-09-07
申请号：US10271936
申请日：2002-10-15
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

48. 发明授权

US06646953B1 Single-clock, strobeless signaling system 失效
标题翻译：单时钟，无频闪信号系统
公开(公告)号：US06646953B1
公开(公告)日：2003-11-11
申请号：US09611936
申请日：2000-07-06
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C800
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

49. 发明授权

US06448828B2 Apparatus and method for edge based duty cycle conversion 有权
公开(公告)号：US06448828B2
公开(公告)日：2002-09-10
申请号：US09978278
申请日：2001-10-15
申请人： Donald C. Stark , Stefanos Sidiropoulos
发明人： Donald C. Stark , Stefanos Sidiropoulos
IPC分类号： H03K3017
CPC分类号： H03K5/1534 , H03K5/151
摘要： A duty cycle converter generating a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The duty cycle converter includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output signal. The signal generator causes the cross-point duty cycle of the first output signal to substantially equal the edge duty cycle of the first input cycle. The signal generator does so by forcing a first time delay between adjacent crossover points of the first and second output signals to be substantially equal to a second time delay between the first transition and the second transition.

50. 发明授权

US06263448B1 Power control system for synchronous memory device 有权
公开(公告)号：US06263448B1
公开(公告)日：2001-07-17
申请号：US09169378
申请日：1998-10-09
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G06F104
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

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