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41. 发明申请

US20100083011A1 INFORMATION PROCESSING DEVICE 失效
标题翻译：信息处理设备
公开(公告)号：US20100083011A1
公开(公告)日：2010-04-01
申请号：US12466696
申请日：2009-05-15
申请人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
发明人： Masafumi ONOUCHI , Hiroyuki Mizuno , Yusuke Kanno , Makoto Saen
IPC分类号： G06F15/76 , G06F1/10 , G06F1/26 , G06F9/02
CPC分类号： G06F1/3203 , G06F1/10 , Y02D10/126
摘要： In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.
摘要翻译：在具有例如六十四个处理器核心，片上存储器，与其连接的总线等的配置中，处理器核心由具有低电压的电源和具有低频率的时钟，总线由高电压电源和高频时钟驱动。每个处理器内核都配有一个总线接口和一个分频器，以便吸收总线与它们中的每一个之间的电源电压差和频率差。分频器从高频时钟产生低频时钟，总线接口提供电平转换功能，数据宽度转换功能，总线与总线接口之间的手抖功能等。

42. 发明授权

US07612604B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07612604B2
公开(公告)日：2009-11-03
申请号：US10429771
申请日：2003-05-06
申请人： Masayuki Miyazaki , Yusuke Kanno , Goichi Ono , Toshinobu Shinbo , Yoshihiko Yasu , Kazumasa Yanagisawa , Takashi Kuraishi
发明人： Masayuki Miyazaki , Yusuke Kanno , Goichi Ono , Toshinobu Shinbo , Yoshihiko Yasu , Kazumasa Yanagisawa , Takashi Kuraishi
IPC分类号： H03K3/01
CPC分类号： H03K19/01707 , H01L27/0928 , H03K19/0016 , H03K2217/0018
摘要： A body bias control system allows for independent design of a functional module, thereby reducing the burden of designing the module. The body bias control system provides a switch circuit having an area in which the body bias is controlled independently of its outside portion, for controlling the supply of body bias in the vicinity of the area. Preferably three types of switches are provided for switching the body bias to suitable levels for a standby mode, a mode of normal operation and a mode of high-speed operation.
摘要翻译：身体偏置控制系统允许功能模块的独立设计，从而减少设计模块的负担。身体偏置控制系统提供了一种开关电路，该开关电路具有独立于其外部部分来控制身体偏压的区域，用于控制该区域附近的身体偏压的供应。优选地，提供三种类型的开关用于将主体偏压切换到用于待机模式，正常操作模式和高速操作模式的适当水平。

43. 发明申请

US20090027984A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090027984A1
公开(公告)日：2009-01-29
申请号：US12242164
申请日：2008-09-30
申请人： HIROYUKI MIZUNO , Takeshi Sakata , Nobuhiro OODAIRA , Takao Watanabe , Yusuke Kanno
发明人： HIROYUKI MIZUNO , Takeshi Sakata , Nobuhiro OODAIRA , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。

44. 发明授权

US07436722B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07436722B2
公开(公告)日：2008-10-14
申请号：US11761642
申请日：2007-06-12
申请人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

45. 发明授权

US07428720B2 Standard cell for a CAD system 失效
标题翻译： CAD系统的标准单元格
公开(公告)号：US07428720B2
公开(公告)日：2008-09-23
申请号：US11797034
申请日：2007-04-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： G06F17/50
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

46. 发明授权

US07375574B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07375574B2
公开(公告)日：2008-05-20
申请号：US11202279
申请日：2005-08-12
申请人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
发明人： Yusuke Kanno , Hiroyuki Mizuno , Kazumasa Yanagisawa
IPC分类号： H03L5/00
CPC分类号： H03K5/1534 , H03K3/356113 , H03K19/018521
摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.
摘要翻译：半导体器件包括差分电平转换器电路，其接收第一信号并输出更大振幅的第二信号。差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

47. 发明申请

US20070291564A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070291564A1
公开(公告)日：2007-12-20
申请号：US11761642
申请日：2007-06-12
申请人： Hiroyuki MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果：位线BL与连接到存储单元的局部位线LBL之间的开关装置用于隔离和耦合这些位线位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BLA的最大幅度电压。读出放大器SA包括包括连接到位线BL的栅极的差分MOS对的第一电路和连接到用于全幅放大的局部位线LBL的第二电路，用于保存数据。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

48. 发明授权

US07242627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07242627B2
公开(公告)日：2007-07-10
申请号：US11363085
申请日：2006-02-28
申请人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki Mizuno , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果。在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

49. 发明申请

US20070136617A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20070136617A1
公开(公告)日：2007-06-14
申请号：US11605362
申请日：2006-11-29
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3293 , G06F1/3203 , H01L21/823462 , Y02D10/122 , Y02D10/126
摘要： There are provided a first processor (11) to be operated at a first operating frequency, a second processor (12) in which a leakage current is reduced more greatly than the first processor and which is operated at a lower second operating frequency than the first operating frequency, and a selecting portion (10) capable of selectively switching an executing destination of an application software into the first processor and the second processor corresponding to a demand operating speed of the application software. The first processor and the second processor can execute an identical instruction set, respectively. It is possible to carry out a high speed processing corresponding to the demand operating speed of the application software and to eliminate a dead current caused by a processing at a speed exceeding the demand operating speed of the application software.
摘要翻译：提供了以第一工作频率操作的第一处理器（11），第二处理器（12），其中泄漏电流比第一处理器更大地减小，并且在比第一工作频率低的第二操作频率下操作以及能够根据应用软件的需求操作速度选择性地将应用软件的执行目的地切换到第一处理器和第二处理器的选择部分（10）。第一处理器和第二处理器可以分别执行相同的指令集。可以执行与应用软件的需求操作速度相对应的高速处理，并且以超过应用软件的需求操作速度的速度消除由处理引起的死电流。

50. 发明授权

US07230477B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07230477B2
公开(公告)日：2007-06-12
申请号：US11296442
申请日：2005-12-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L2/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

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