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41. 发明申请

US20080197500A1 INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP 失效
标题翻译：具有双层金属盖的互连结构
公开(公告)号：US20080197500A1
公开(公告)日：2008-08-21
申请号：US11675705
申请日：2007-02-16
申请人： Chih-Chao Yang , Kaushik Chanda , Ping-Chuan Wang
发明人： Chih-Chao Yang , Kaushik Chanda , Ping-Chuan Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76856 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.
摘要翻译：提供了制造具有双层金属盖的互连结构的结构和方法。在一个实施例中，该方法包括在电介质材料层中形成互连特征; 以及在所述互连特征的顶表面上形成双层金属帽。该方法还包括沉积介电覆盖层的覆盖层，其中沉积覆盖电介质材料层的暴露表面和双层金属帽的表面。双层金属盖包括形成在互连特征的导电表面上的金属覆盖层; 以及形成在金属覆盖层的顶部上的金属氮化物。还描述了具有形成在电介质层中的互连特征的互连结构; 形成在互连特征的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。

42. 发明申请

US20070063348A1 METHOD AND STRUCTURE OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS 有权
标题翻译：形成互连的方法和结构，包括具有拉伸应力的电介质盖
公开(公告)号：US20070063348A1
公开(公告)日：2007-03-22
申请号：US11162666
申请日：2005-09-19
申请人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
发明人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译：提供了互连结构及其制造方法。互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

43. 发明申请

US20070037403A1 VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US20070037403A1
公开(公告)日：2007-02-15
申请号：US11161599
申请日：2005-08-09
申请人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

44. 发明授权

US08298948B2 Capping of copper interconnect lines in integrated circuit devices 有权
标题翻译：在集成电路器件中封装铜互连线
公开(公告)号：US08298948B2
公开(公告)日：2012-10-30
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

45. 发明授权

US08232645B2 Interconnect structures, design structure and method of manufacture 有权
标题翻译：互连结构，设计结构和制造方法
公开(公告)号：US08232645B2
公开(公告)日：2012-07-31
申请号：US12191522
申请日：2008-08-14
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
IPC分类号： H01L23/48
CPC分类号： H01L23/5329 , H01L21/76846 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing. The metal interconnect is formed in a dielectric material. A metal cap is selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.
摘要翻译：提供了一种互连结构，其基本上消除了电迁移（EM）损伤，设计结构和制造方法。金属互连形成在电介质材料中。金属盖对金属互连有选择性。金属盖包括RuX，其中X在硼，磷或硼和磷的组合。

46. 发明授权

US07314786B1 Metal resistor, resistor material and method 有权
标题翻译：金属电阻，电阻材料及方法
公开(公告)号：US07314786B1
公开(公告)日：2008-01-01
申请号：US11420121
申请日：2006-06-16
申请人： Chih-Chao Yang , Kaushik Chanda , Shyng-Tsong Chen
发明人： Chih-Chao Yang , Kaushik Chanda , Shyng-Tsong Chen
IPC分类号： H01L21/338 , H01L21/8234 , H01L21/8222
CPC分类号： H01L29/86 , H01L23/5228 , H01L2924/0002 , H04W36/08 , H04W88/08 , H04W88/18 , H01L2924/00
摘要： A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.
摘要翻译：公开了一种金属电阻器和电阻器材料以及形成金属电阻器的方法。金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2/2），碳（C），钽（ Ta），钛（Ti）和钨（W），以及输入硅（Si），氮（N 2/2），碳（C），钽（Ta），钛（Ti）和钨（W）。该方法比常规方法复杂得多，允许通过灌注材料的量控制电阻，并且与传统的BEOL方法兼容。

47. 发明申请

US20070259519A1 INTERCONNECT METALLIZATION PROCESS WITH 100% OR GREATER STEP COVERAGE 审中-公开
标题翻译：具有100％或更大步骤覆盖的互连金属化工艺
公开(公告)号：US20070259519A1
公开(公告)日：2007-11-08
申请号：US11381194
申请日：2006-05-02
申请人： Chih-Chao Yang , Kaushik Chanda
发明人： Chih-Chao Yang , Kaushik Chanda
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , C23C14/046 , H01L21/2855 , H01L21/76843 , H01L21/76846
摘要： An interconnect structure with a thicker barrier material coverage at the sidewalls of a feature as compared to the thickness of said barrier material at the feature bottom as well as a method of fabricating such an interconnect structure are provided. The interconnect structure of the present invention has improved technology extendibility for the semiconductor industry as compared with prior art interconnect structure in which the barrier material is formed by a conventional PVD process, a conventional ionized plasma deposition, CVD or ALD. In accordance with the present invention, an interconnect structure having a barrier material thickness at the feature sidewalls (wt) greater than the barrier material thickness at the feature bottom (ht) is provided. That is, the wt/ht ratio is equal to, or greater than, 100% in the inventive interconnect structure.
摘要翻译：提供了与特征底部处的所述阻挡材料的厚度相比，在特征侧壁处具有较厚阻挡材料覆盖的互连结构以及制造这种互连结构的方法。与现有技术的互连结构相比，本发明的互连结构具有改进的技术可扩展性，其中阻挡材料通过常规PVD工艺，常规电离等离子体沉积，CVD或ALD形成。根据本发明，具有大于特征底部处的阻挡材料厚度的特征侧壁处的阻挡材料厚度（w ）。也就是说，本发明的互连结构中的比例等于或大于100％。

48. 发明授权

US07906428B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

49. 发明授权

US07528065B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US07528065B2
公开(公告)日：2009-05-05
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

50. 发明申请

US20080308801A1 STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STOCHASTIC集成电路个性化结构
公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

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