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1. 发明申请

US20080308801A1 STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STOCHASTIC集成电路个性化结构
公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

2. 发明申请

US20080157314A1 STRUCTURE AND METHOD FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STCCHASTIC集成电路个性化的结构与方法
公开(公告)号：US20080157314A1
公开(公告)日：2008-07-03
申请号：US11619196
申请日：2007-01-03
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/02
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

3. 发明授权

US07544578B2 Structure and method for stochastic integrated circuit personalization 失效
标题翻译：随机集成电路个性化的结构与方法
公开(公告)号：US07544578B2
公开(公告)日：2009-06-09
申请号：US11619196
申请日：2007-01-03
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/20
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

4. 发明授权

US07838873B2 Structure for stochastic integrated circuit personalization 失效
标题翻译：随机集成电路个性化的结构
公开(公告)号：US07838873B2
公开(公告)日：2010-11-23
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L47/00 , H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

5. 发明授权

US07544602B2 Method and structure for ultra narrow crack stop for multilevel semiconductor device 失效
标题翻译：多级半导体器件超窄裂纹停止的方法和结构
公开(公告)号：US07544602B2
公开(公告)日：2009-06-09
申请号：US11693033
申请日：2007-03-29
申请人： Lawrence A. Clevenger , Matthew E. Colburn , William F. Landers , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , William F. Landers , Wai-Kin Li
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.
摘要翻译：一种集成电路设计和制造方法，更具体地说，具有用于多电平电平装置的超窄裂缝停止的半导体结构及其制造方法。该结构包括具有连接到底层互连的第一连接的第一介电层和具有连接到第一连接的第二连接的第二介电层。止挡间隙结构延伸穿过第一介电层和第二介电层，并且具有大约小于1μm的宽度。

6. 发明授权

US08772941B2 Circuit structure with low dielectric constant regions 有权
标题翻译：具有低介电常数区域的电路结构
公开(公告)号：US08772941B2
公开(公告)日：2014-07-08
申请号：US12206314
申请日：2008-09-08
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译：一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

7. 发明授权

US07692308B2 Microelectronic circuit structure with layered low dielectric constant regions 失效
标题翻译：微电子电路结构具有层状低介电常数区域
公开(公告)号：US07692308B2
公开(公告)日：2010-04-06
申请号：US12256735
申请日：2008-10-23
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L29/40
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.
摘要翻译：电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

8. 发明申请

US20090072410A1 MICROELECTRONIC CIRCUIT STRUCTURE WITH LAYERED LOW DIELECTRIC CONSTANT REGIONS 失效
标题翻译：具有层状低介电常数区域的微电路电路结构
公开(公告)号：US20090072410A1
公开(公告)日：2009-03-19
申请号：US12256735
申请日：2008-10-23
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L23/52
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.
摘要翻译：电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

9. 发明授权

US07439172B2 Circuit structure with low dielectric constant regions and method of forming same 有权
标题翻译：具有低介电常数区域的电路结构及其形成方法
公开(公告)号：US07439172B2
公开(公告)日：2008-10-21
申请号：US11623478
申请日：2007-01-16
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译：一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

10. 发明申请

US20080171432A1 Circuit Structure with Low Dielectric Constant Regions and Method of Forming Same 有权
标题翻译：具有低介电常数区域的电路结构及其形成方法
公开(公告)号：US20080171432A1
公开(公告)日：2008-07-17
申请号：US11623478
申请日：2007-01-16
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译：一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

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