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41. 发明授权

US07423446B2 Characterization array and method for determining threshold voltage variation 失效
标题翻译：用于确定阈值电压变化的表征阵列和方法
公开(公告)号：US07423446B2
公开(公告)日：2008-09-09
申请号：US11462186
申请日：2006-08-03
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2621 , G01R31/275
摘要： A method for determining threshold voltage variation rapidly provides accurate threshold voltage distribution values for process verification and improvement. The method operates a characterization away including a circuit for imposing a fixed drain-source voltage and a constant channel current at individual devices within the array, while sensing the source voltage of the individual device. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.
摘要翻译：用于确定阈值电压变化的方法快速提供用于过程验证和改进的精确的阈值电压分布值。该方法操作表征，包括用于在阵列内的各个器件处施加固定的漏极 - 源极电压和恒定沟道电流的电路，同时检测各个器件的源极电压。阈值电压的统计分布直接由源电压分布确定，通过将每个源极电压抵消通过完全表征阵列内的一个或多个器件而确定的值。所得到的方法避免了对阵列内的每个器件进行表征的必要性，从而显着地减少了测量时间。

42. 发明申请

US20080195337A1 Scannable Virtual Rail Method and Ring Oscillator Circuit for Measuring Variations in Device Characteristics 失效
标题翻译：可扫描的虚拟轨道方法和环形振荡器电路，用于测量器件特性的变化
公开(公告)号：US20080195337A1
公开(公告)日：2008-08-14
申请号：US11673025
申请日：2007-02-09
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/28 , H03K3/03 , G06F19/00 , G01R23/02
CPC分类号： G01R31/2884 , G01R31/318577 , H03K3/0315 , H03K2005/00058 , H03K2005/00234
摘要： A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.
摘要翻译：用于测量器件特性变化的可扫描虚拟轨迹法和环形振荡器电路提供了研究随机器件特性变化以及使用环形振荡器频率测量的N沟道和P沟道器件之间的系统差异的能力。环形振荡器通过由可编程源控制的多个晶体管连接到实际电源轨的至少一个虚拟电源轨来操作。晶体管沿着环形振荡器元件的物理分布物理分布，并且可以依次启用晶体管，并测量环形振荡器频率的变化。可以通过使用具有相应P沟道和N沟道控制晶体管的正和负虚拟电源轨来研究环形振荡器频率测量产生关于晶体管与N沟道与P沟道变化之间变化的信息。

43. 发明授权

US09471732B2 Equivalent device statistical modeling for bitline leakage modeling 有权
公开(公告)号：US09471732B2
公开(公告)日：2016-10-18
申请号：US13616991
申请日：2012-09-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

44. 发明授权

US08799732B2 Methodology for correlated memory fail estimations 有权
标题翻译：相关内存失败估算方法
公开(公告)号：US08799732B2
公开(公告)日：2014-08-05
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/00 , G06F11/00 , G11C29/08 , G06F17/18
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

45. 发明授权

US08676516B2 Test circuit for bias temperature instability recovery measurements 失效
标题翻译：用于偏置温度不稳定性恢复测量的测试电路
公开(公告)号：US08676516B2
公开(公告)日：2014-03-18
申请号：US13524208
申请日：2012-06-15
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L3/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法和测试电路提供测量，以准确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

46. 发明申请

US20130212444A1 METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS 有权
标题翻译：相关记忆失败估算方法
公开(公告)号：US20130212444A1
公开(公告)日：2013-08-15
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

47. 发明授权

US08365118B2 Broken-spheres methodology for improved failure probability analysis in multi-fail regions 有权
标题翻译：用于改善多故障区域故障概率分析的破碎球方法
公开(公告)号：US08365118B2
公开(公告)日：2013-01-29
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F9/455
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

48. 发明申请

US20120319675A1 CALIBRATION OF NON-CONTACT VOLTAGE SENSORS 失效
标题翻译：非接触式电压传感器的校准
公开(公告)号：US20120319675A1
公开(公告)日：2012-12-20
申请号：US13159568
申请日：2011-06-14
申请人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Sani R. Nassif
发明人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Sani R. Nassif
IPC分类号： G01R35/00 , G01R1/20
CPC分类号： G01R35/02 , G01R15/207
摘要： Calibration of a non-contact voltage sensor provides improved accuracy for measuring voltage on a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined voltage is imposed on a first voltage sensing conductor integrated in the non-contact voltage sensor, while a voltage on a second voltage sensing conductor is measured using a circuit of predetermined input impedance. The capacitance between the wire and each of the voltage sensing conductors may be the same, so that in measurement mode, when the first and second voltage sensing conductors are coupled together, the effective series capacitance provided in combination with the predetermined input impedance is four times as great. The results of the voltage measurement made in the calibration mode can thereby be used to adjust subsequent voltage measurements made in measurement mode with the first and second voltage sensing conductors combined in parallel.
摘要翻译：非接触式电压传感器的校准为测量诸如AC分支电路线的导体上的电压提供了更高的精度。在校准模式中，在集成在非接触电压传感器中的第一电压感测导体上施加预定电压，同时使用预定输入阻抗的电路测量第二电压感测导体上的电压。导线与每个电压感测导体之间的电容可以相同，使得在测量模式下，当第一和第二电压感测导体耦合在一起时，与预定输入阻抗组合提供的有效串联电容是四倍一样好因此，在校准模式中进行的电压测量的结果可用于调节在测量模式下进行的随后的电压测量，其中第一和第二电压感测导体并联组合。

49. 发明申请

US20120266111A1 Gradient-Based Search Mechanism for Optimizing Photolithograph Masks 审中-公开
公开(公告)号：US20120266111A1
公开(公告)日：2012-10-18
申请号：US13531703
申请日：2012-06-25
申请人： Ying Liu , Sani R. Nassif , Xiaokang Shi
发明人： Ying Liu , Sani R. Nassif , Xiaokang Shi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α2 is selected where the initial value of α2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

50. 发明申请

US20100262414A1 METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS 有权
标题翻译：相关记忆失败估算方法
公开(公告)号：US20100262414A1
公开(公告)日：2010-10-14
申请号：US12422420
申请日：2009-04-13
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/10
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

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