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41. 发明授权

US07397259B1 Method and apparatus for statistical CMOS device characterization 失效
标题翻译：用于统计CMOS器件表征的方法和装置
公开(公告)号：US07397259B1
公开(公告)日：2008-07-08
申请号：US11736146
申请日：2007-04-17
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26 , G01R33/00 , G01R31/02
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线进行操作的输入/输出引脚。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

42. 发明授权

US08782573B2 Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis 失效
$Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis$
标题翻译：基于衍射图案分析的重新定位集成电路布局的解决方案
公开(公告)号：US08782573B2
公开(公告)日：2014-07-15
申请号：US13600319
申请日：2012-08-31
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70441
摘要： A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.
摘要翻译：公开了一种用于重新定位集成电路（IC）布局的计算机实现的方法。在一个实施例中，该方法包括生成包括一组衍射级的IC布局的衍射图案，该IC布局包括由一组目标边缘定义的一组特征，用优点函数分析衍射图案以估计可印刷性的IC布局，监视优值函数的值的变化作为所述一组目标边缘中的至少一个的位置在一个范围内被调整，并且基于所述优值函数的监视来重新定位所述一组目标边缘。

43. 发明授权

US08647893B1 Method for post decomposition density balancing in integrated circuit layouts, related system and program product 有权
标题翻译：集成电路布局中后分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US08647893B1
公开(公告)日：2014-02-11
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

44. 发明申请

US20130297292A1 High Bandwidth Parsing of Data Encoding Languages 有权
标题翻译：数据编码语言的高带宽分析
公开(公告)号：US20130297292A1
公开(公告)日：2013-11-07
申请号：US13464384
申请日：2012-05-04
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/27 , G06F3/00
CPC分类号： G06F17/272
摘要： A mechanism is provided for accelerating data exchange language parsing. An input data stream is loaded into a first in, first out (FIFO) memory. A tokenization bit corresponding to a next byte to be read is extracted from a FIFO. A determination is made as to whether the tokenization bit corresponding to the next byte to be read from the FIFO indicates a control character or a non-control character located in an associated FIFO memory location in the FIFO. Responsive to the tokenization bit indicating the control character, the control character that causes a state change in a state machine is processed. Responsive to the tokenization bit indicating the non-control character, a length associated with the tokenized bit is identified and a set of non-control characters that do not cause a state change in the state machine are processed based on the length associated with the tokenized bit.
摘要翻译：提供了一种加速数据交换语言解析的机制。输入数据流被加载到先进先出（FIFO）存储器中。从FIFO中提取与要读取的下一个字节对应的令牌化位。确定与从FIFO读取的下一个字节相对应的标记位是否指示位于FIFO中的相关FIFO存储器位置中的控制字符或非控制字符。响应于表示控制字符的标记位，处理导致状态机状态变化的控制字符。响应于指示非控制字符的标记位，识别与标记化位相关联的长度，并且基于与标记化位相关联的长度来处理在状态机中不导致状态改变的一组非控制字符位。

45. 发明授权

US08230372B2 Retargeting for electrical yield enhancement 失效
标题翻译：重新定位用于电收益增强
公开(公告)号：US08230372B2
公开(公告)日：2012-07-24
申请号：US12630216
申请日：2009-12-03
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.
摘要翻译：提供了用于光刻布局的电屈服增强重定向的机制。对一组目标图案执行光学邻近校正，以便产生一组光学邻近校正掩模形状。针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。确定一组目标图案中的一组形状中的至少一种形状的电屈服敏感度。还基于形状的电屈服敏感度来确定该组形状中的至少一个形状中的每一个的重定向的量和方向。基于重定向的数量和方向，为至少一个形状中的每个形状生成具有重定向边缘的新集合的目标图案。

46. 发明授权

US08151240B2 Effective gate length circuit modeling based on concurrent length and mobility analysis 有权
标题翻译：基于并发长度和移动性分析的有效栅长电路建模
公开(公告)号：US08151240B2
公开(公告)日：2012-04-03
申请号：US12416222
申请日：2009-04-01
申请人： Kanak B. Agarwal , Vivek Joshi
发明人： Kanak B. Agarwal , Vivek Joshi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G06F17/5036
摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
摘要翻译：公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。模拟器计算每个切片的应力分布。模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。模拟器基于长度电流确定MOS栅极的有效长度。

47. 发明申请

US20110138342A1 Retargeting for Electrical Yield Enhancement 失效
标题翻译：重新定位电收益增强
公开(公告)号：US20110138342A1
公开(公告)日：2011-06-09
申请号：US12630216
申请日：2009-12-03
申请人： Kanak B. Agarwal
发明人： Kanak B. Agarwal
IPC分类号： G06F17/50 , G21K5/10
CPC分类号： G03F1/36
摘要： A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.
摘要翻译：提供了用于光刻布局的电屈服增强重定向的机制。对一组目标图案执行光学邻近校正，以便产生一组光学邻近校正掩模形状。针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。确定一组目标图案中的一组形状中的至少一种形状的电屈服敏感度。还基于形状的电屈服敏感度来确定该组形状中的至少一个形状中的每一个的重定向的量和方向。基于重定向的数量和方向，为至少一个形状中的每个形状生成具有重定向边缘的新集合的目标图案。

48. 发明申请

US20100333049A1 Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography 有权
标题翻译：用于亚波长光刻的布局图案的基于模型的重新定位
公开(公告)号：US20100333049A1
公开(公告)日：2010-12-30
申请号：US12492301
申请日：2009-06-26
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.
摘要翻译：提供了用于光刻布局的基于模型的重新定位的机制。对预定次数的迭代的一组目标图案执行光学邻近校正，直到计数器值超过最大预定迭代次数为了产生一组光学邻近校正掩模形状。响应于计数器值超过最大预定迭代次数，针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。在目标形状集上执行归一化图像对数斜率（NILS）提取，并使用该组光刻轮廓来产生NILS值。基于NILS值响应于NILS值不能在预定限度内修改目标模式集合。重复这些步骤，直到NILS值在预定限度内。

49. 发明申请

US20100327892A1 Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

50. 发明授权

US07834649B2 Method and apparatus for statistical CMOS device characterization 失效
标题翻译：用于统计CMOS器件表征的方法和装置
公开(公告)号：US07834649B2
公开(公告)日：2010-11-16
申请号：US12779038
申请日：2010-05-12
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

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