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41. 发明申请

US20110034027A1 Structure and Process for the Formation of TSVs 有权
标题翻译： TSV形成的结构和过程
公开(公告)号：US20110034027A1
公开(公告)日：2011-02-10
申请号：US12910621
申请日：2010-10-22
申请人： Chen-Cheng Kuo , Kai-Ming Ching , Chen Chen-Shien
发明人： Chen-Cheng Kuo , Kai-Ming Ching , Chen Chen-Shien
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L2224/13009 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.
摘要翻译：集成电路结构包括半导体衬底; 在所述半导体衬底上的互连结构，其中所述互连结构包括顶部金属间电介质（IMD）; 穿过所述互连结构进入所述半导体衬底的开口; 开幕式的指挥; 以及具有彼此物理连接的垂直部分和水平部分的隔离层。垂直部分位于开口的侧壁上。水平部分直接在互连结构上方。集成电路结构在顶部IMD和隔离层的水平部分之间垂直地没有钝化层。

42. 发明申请

US20090160058A1 Structure and process for the formation of TSVs 有权
标题翻译： TSV形成的结构和过程
公开(公告)号：US20090160058A1
公开(公告)日：2009-06-25
申请号：US12152381
申请日：2008-05-14
申请人： Chen-Cheng Kuo , Kai-Ming Ching , Chen Chen-Shien
发明人： Chen-Cheng Kuo , Kai-Ming Ching , Chen Chen-Shien
IPC分类号： H01L23/522
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L2224/13009 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.
摘要翻译：集成电路结构包括半导体衬底; 在所述半导体衬底上的互连结构，其中所述互连结构包括顶部金属间电介质（IMD）; 穿过所述互连结构进入所述半导体衬底的开口; 开幕式的指挥; 以及具有彼此物理连接的垂直部分和水平部分的隔离层。垂直部分位于开口的侧壁上。水平部分直接在互连结构上方。集成电路结构在顶部IMD和隔离层的水平部分之间垂直地没有钝化层。

43. 发明申请

US20090051039A1 THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE 有权
标题翻译：通过半导体器件通过衬底
公开(公告)号：US20090051039A1
公开(公告)日：2009-02-26
申请号：US11844650
申请日：2007-08-24
申请人： Chen-Cheng Kuo , Chen Chen-Shien , Kai-Ming Ching , Chih-Hua Chen
发明人： Chen-Cheng Kuo , Chen Chen-Shien , Kai-Ming Ching , Chih-Hua Chen
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via.
摘要翻译：提供了包括具有前表面和后表面的基板的半导体器件。多个互连层形成在前表面上并具有与基板的前表面相对的第一表面。锥形轮廓通孔从多个互连层的第一表面延伸到基底的后表面。在一个实施例中，在衬底上形成绝缘层并且包括开口，并且其中开口包括提供与锥形轮廓通孔接触的导电材料。

44. 发明授权

US07468321B2 Application of impressed-current cathodic protection to prevent metal corrosion and oxidation 有权
标题翻译：应用电流阴极保护，防止金属腐蚀和氧化
公开(公告)号：US07468321B2
公开(公告)日：2008-12-23
申请号：US11382500
申请日：2006-05-10
申请人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
发明人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L21/76838 , H01L24/11 , H01L24/12 , H01L2223/54453 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/30105 , H01L2224/05647 , H01L2924/00014 , H01L2224/05671 , H01L2224/05124 , H01L2224/05147
摘要： A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
摘要翻译：提供了一种新的方法来处理金属，特别是铜，以防止这些金属暴露表面的损坏。在半导体加工的步骤中，导致将金属表面暴露于具有pH值的湿物质的步骤中，向暴露的金属施加电压。施加电压的值可以根据湿物质的pH常数的值来选择，使得暴露的金属表面被保护免受湿物质的碱性影响。

45. 发明申请

US20080286938A1 Semiconductor device and fabrication methods thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080286938A1
公开(公告)日：2008-11-20
申请号：US11798432
申请日：2007-05-14
申请人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
发明人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
IPC分类号： H01L21/30
CPC分类号： H01L21/78 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2924/00014
摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.
摘要翻译：一种封装半导体器件的方法。提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。沿着划线区域锯切基板，通过开口。在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。图案化第一结构层以在第一划线区域内形成第一开口。提供了包括分别由第二划线区域分隔的多个第二模具的第二衬底，其中至少一个第二结构层覆盖在衬底上。图案化第二结构层以在第二划线区域内形成第二开口。第一基板和第二基板被接合以形成堆叠结构。沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

46. 发明申请

US20070028445A1 Fluxless bumping process 有权
标题翻译：无通风碰撞过程
公开(公告)号：US20070028445A1
公开(公告)日：2007-02-08
申请号：US11581122
申请日：2006-10-13
申请人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
发明人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
IPC分类号： B23K31/02
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49149 , Y10T29/49179 , H01L2924/00014 , H01L2924/00
摘要： A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
摘要翻译：一种方法，包括提供包括接合焊盘的半导体器件和覆盖在焊盘上的凸块下金属。在凸块下冶金上形成焊料结构，其中焊料结构包括包含氧化锡的外层。从CF 4和SF 6 6中的至少一个生成等离子体，并将焊料结构暴露于等离子体。加热焊料结构并对其进行冷却以在半导体器件上提供焊料凸块。

47. 发明授权

US06926818B1 Method to enhance the adhesion between dry film and seed metal 有权
标题翻译：提高干膜和种子金属之间粘附的方法
公开(公告)号：US06926818B1
公开(公告)日：2005-08-09
申请号：US09961557
申请日：2001-09-24
申请人： Yih-Ann Lin , Tung-Heng Shie , Kai-Ming Ching , Sheng-Liang Pan , Kuo-Liang Lu
发明人： Yih-Ann Lin , Tung-Heng Shie , Kai-Ming Ching , Sheng-Liang Pan , Kuo-Liang Lu
IPC分类号： C25D5/02
CPC分类号： C25D5/022 , H01L2224/0401 , H01L2224/05557
摘要： A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug. The patterned dry film resist is removed from the conductive structure. The conductive plug is reflowed to form the bump structure.
摘要翻译：通过使用电镀液形成凸点结构的方法，包括以下步骤。提供具有上覆导电结构的基板。在导电结构上形成图案化的干膜抗蚀剂。图案化的干膜抗蚀剂具有暴露导电结构的一部分的沟槽。在界面处附着在导电结构上的图案化的干膜抗蚀剂。通过增加图案化的干膜抗蚀剂在界面处的导电结构的粘附性的处理来处理该结构。通过使用电镀溶液，导电插塞在沟槽内的导电结构的暴露部分之上。图案化的干膜抗蚀剂在界面处增加了对导电结构的粘附，防止电镀溶液在形成导电插塞期间渗透图案化的干膜抗蚀剂和导电结构的界面。从导电结构去除图案化的干膜抗蚀剂。导电塞被回流以形成凸块结构。

48. 发明授权

US06802250B2 Stencil design for solder paste printing 失效
标题翻译：焊膏印刷模板设计
公开(公告)号：US06802250B2
公开(公告)日：2004-10-12
申请号：US10151377
申请日：2002-05-20
申请人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen
发明人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen
IPC分类号： B41N124
CPC分类号： B41N1/24 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K3/1225 , H01L2924/00 , H01L2224/48
摘要： A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.
摘要翻译：公开了用于焊膏印刷或其它金属模版印刷的模板设计。用于将半导体晶片凸起的半导体晶片上的焊料模版印刷的模板包括基板。衬底具有限定在其中的孔，其基本成形为对应于并接受半导体晶片。基板的内部边缘围绕孔，并且具有上半边缘，半导体晶片定位在该上边缘上。围绕孔的衬底的内部边缘的上唇基本上防止焊料在模版印刷焊料期间流到半导体晶片的侧面和底部。在一个实施例中，上唇的横截面形状可以是矩形，而在另一个实施例中是三角形。

49. 发明授权

US06797075B2 Ferris wheel-like stripping or cleaning mechanism for semiconductor fabrication 失效
标题翻译：用于半导体制造的摩天轮式剥离或清洁机构
公开(公告)号：US06797075B2
公开(公告)日：2004-09-28
申请号：US10143053
申请日：2002-05-09
申请人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee
发明人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee
IPC分类号： B08B104
CPC分类号： H01L21/67313 , B08B3/10 , H01L21/67057
摘要： A Ferris wheel-like stripping or cleaning mechanism that can be used in semiconductor fabrication, such as in photoresist or other stripping, or wafer or other cleaning, is disclosed. A stripping mechanism can include a container to hold a chemical, such as a photoresist stripping chemical, a wafer cleaning chemical, or another type of chemical. The mechanism can also include a component to move semiconductor wafers through the chemical in the container in a Ferris wheel-like motion. The component may include wafer holders for the wafers that are swivably mounted about an axis of rotation. As the one or more wafer holders rotate about the axis of rotation through the chemical in the container, the wafer holders remain in a substantially constant vertical and horizontal orientation.
摘要翻译：公开了可用于半导体制造中的摩擦轮式剥离或清洁机构，例如在光致抗蚀剂或其它剥离，或晶片或其它清洁中。剥离机构可以包括容纳化学物质的容器，例如光刻胶剥离化学品，晶片清洁化学品或其它类型的化学品。该机构还可以包括以摩天轮状运动将半导体晶片移动通过容器中的化学物质的部件。组件可以包括围绕旋转轴线可旋转地安装的用于晶片的晶片保持器。当一个或多个晶片保持器围绕容器中的化学物质的旋转轴旋转时，晶片保持器保持基本恒定的垂直和水平取向。

50. 发明授权

US06743660B2 Method of making a wafer level chip scale package 有权
标题翻译：制造晶圆级芯片级封装的方法
公开(公告)号：US06743660B2
公开(公告)日：2004-06-01
申请号：US10045783
申请日：2002-01-12
申请人： Hsin-Hui Lee , Chia-Fu Lin , Chao-Yuan Su , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen
发明人： Hsin-Hui Lee , Chia-Fu Lin , Chao-Yuan Su , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen
IPC分类号： H01L2148
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05647 , H01L2224/11334 , H01L2224/1147 , H01L2224/13022 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , Y10T29/49147 , Y10T29/49151 , Y10T29/49204 , Y10T29/49222 , H01L2924/00 , H01L2924/00014
摘要： A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.
摘要翻译：在半导体晶片或倒装芯片等基板上形成凸点的方法。该方法包括提供具有接触焊盘并具有上钝化层的半导体器件的动作，并且在上钝化层中形成的开口暴露接触焊盘的一部分。在上钝化层和接触焊盘上沉积凸块下冶金。导电再分布迹线沉积在凸块下金属之上。沉积，图案化和显影光致抗蚀剂层以提供选择性地保护导电再分布迹线和凸块下冶金的部分。移除不被光致抗蚀剂保护的导电再分布迹线和凸块下冶金的多余部分。

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