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41. 发明授权

US07232757B2 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US07232757B2
公开(公告)日：2007-06-19
申请号：US10811927
申请日：2004-03-30
申请人： Junji Noguchi , Naohumi Ohashi , Tatsuyuki Saito
发明人： Junji Noguchi , Naohumi Ohashi , Tatsuyuki Saito
IPC分类号： H01L21/44
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/02274 , H01L21/3105 , H01L21/3185 , H01L21/3212 , H01L21/67219 , H01L21/76808 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
摘要翻译：通过使用CMP的抛光来形成嵌入在氧化硅膜的互连槽中的Cu互连，以提高使用Damascene方法形成的铜互连的绝缘击穿电阻，并且在CMP后的清洗步骤中，氧化硅膜的表面并且通过还原等离子体（氨等离子体）处理Cu互连。随后，形成连续的盖膜（氮化硅膜）而没有真空断裂。

42. 发明授权

US06764950B2 Fabrication method for semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06764950B2
公开(公告)日：2004-07-20
申请号：US09825946
申请日：2001-04-05
申请人： Junji Noguchi , Naohumi Ohashi , Tatsuyuki Saito
发明人： Junji Noguchi , Naohumi Ohashi , Tatsuyuki Saito
IPC分类号： H01L2144
CPC分类号： H01L21/0217 , H01L21/02063 , H01L21/02074 , H01L21/02164 , H01L21/02274 , H01L21/3105 , H01L21/3185 , H01L21/3212 , H01L21/67219 , H01L21/76808 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
摘要翻译：通过使用CMP的抛光来形成嵌入在氧化硅膜的互连槽中的Cu互连，以提高使用Damascene方法形成的铜互连的绝缘击穿电阻，并且在CMP后的清洗步骤中，氧化硅膜的表面并且通过还原等离子体（氨等离子体）处理Cu互连。随后，形成连续的盖膜（氮化硅膜）而没有真空断裂。

43. 发明申请

US20070004189A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20070004189A1
公开(公告)日：2007-01-04
申请号：US11516762
申请日：2006-09-07
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/44
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

44. 发明授权

US07084063B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07084063B2
公开(公告)日：2006-08-01
申请号：US10742932
申请日：2003-12-23
申请人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
发明人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
IPC分类号： H01L21/302
CPC分类号： H01L21/76843 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/32136 , H01L21/76801 , H01L21/76808 , H01L21/76832 , H01L21/76838 , H01L21/76849 , H01L21/76862 , H01L21/76864 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
摘要翻译：通过使用镶嵌技术形成的铜互连在介电击穿强度（可靠性）方面得到改善。在后CMP清洗中，碱洗，由于氢退火等引起的脱氧处理以及酸清洗依次进行。在CMP后清洗之后，在形成用于盖膜的绝缘膜之前，在半导体衬底上进行氢等离子体和氨等离子体处理。以这种方式，在由具有低介电常数的绝缘材料构成的层间绝缘膜中形成铜基掩埋互连。

45. 发明申请

US20050118809A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050118809A1
公开(公告)日：2005-06-02
申请号：US10981662
申请日：2004-11-05
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/304 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

46. 发明授权

US06723631B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06723631B2
公开(公告)日：2004-04-20
申请号：US09965220
申请日：2001-09-28
申请人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
发明人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/32136 , H01L21/76801 , H01L21/76808 , H01L21/76832 , H01L21/76838 , H01L21/76849 , H01L21/76862 , H01L21/76864 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
摘要翻译：通过使用镶嵌技术形成的铜互连在介电击穿强度（可靠性）方面得到改善。在后CMP清洗中，碱洗，由于氢退火等引起的脱氧处理和酸清洗按顺序进行。在CMP后清洗之后，在形成用于盖膜的绝缘膜之前，在半导体衬底上进行氢等离子体和氨等离子体处理。以这种方式，在由具有低介电常数的绝缘材料构成的层间绝缘膜中形成铜基掩埋互连。

47. 发明授权

US08368151B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08368151B2
公开(公告)日：2013-02-05
申请号：US12644461
申请日：2009-12-22
申请人： Kenji Miyakoshi , Shinichiro Wada , Junji Noguchi , Koichiro Miyamoto , Masaya Iida , Masafumi Suefuji
发明人： Kenji Miyakoshi , Shinichiro Wada , Junji Noguchi , Koichiro Miyamoto , Masaya Iida , Masafumi Suefuji
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823412
摘要： When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage.
摘要翻译：当源极和漏极形成对称结构的多个阈值电压的MOS晶体管被安装在同一衬底上时，相对于每个MOS晶体管中的源极和漏极的交换来提供电对称特性。具有大阈值电压的MOS晶体管具有卤素扩散区域，并且不对具有小阈值电压的MOS晶体管进行晕圈注入。

48. 发明授权

US08122405B2 Delay adjusting method and LSI that uses air-gap wiring 有权
标题翻译：延时调整方法和使用气隙接线的LSI
公开(公告)号：US08122405B2
公开(公告)日：2012-02-21
申请号：US12253469
申请日：2008-10-17
申请人： Takashi Matsumoto , Junji Noguchi , Takayuki Oshima
发明人： Takashi Matsumoto , Junji Noguchi , Takayuki Oshima
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void formation inhibition zone is set up in a part or all of a spacing (inter-wiring spacing) between an optimization-target wiring which needs a further delay time of a signal and clock and an adjacent wiring adjacent to the optimization-target wiring having a spacing within a specified wiring spacing, and an insulating film is formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring in the void formation inhibition zone, and voids are formed in a spacing (inter-wiring spacing) between the optimization-target wiring and the adjacent wiring outside the void formation inhibition zone.
摘要翻译：提供一种制造半导体集成电路器件的方法，其能够进行定时优化，而不增加制造工艺并增加成本和TAT。确定定时约束违规的存在，并且当检测到定时约束违规时，为了解决违规，在优化目标之间的间隔（布线间距）的一部分或全部中建立空隙形成禁止区需要进一步延迟信号和时钟的延迟时间的布线以及与优选目标布线相邻的相邻布线，其间距在指定布线间距内，并且绝缘膜以优选的间隔（布线间距）形成在空隙形成抑制区域中的目标布线和相邻布线，并且在空隙形成抑制区外部的优化目标布线和相邻布线之间的间隔（布线间距）形成空隙。

49. 发明申请

US20110140275A1 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US20110140275A1
公开(公告)日：2011-06-16
申请号：US12929782
申请日：2011-02-15
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L23/532
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

50. 发明申请

US20060183317A1 Semiconductor device and a method of manufacturing the same 审中-公开
公开(公告)号：US20060183317A1
公开(公告)日：2006-08-17
申请号：US11401287
申请日：2006-04-11
申请人： Junji Noguchi , Tsuyoshi Fujiwara
发明人： Junji Noguchi , Tsuyoshi Fujiwara
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76801 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76832 , H01L21/76834
摘要： Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.

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