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41. 发明授权

US08993386B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08993386B2
公开(公告)日：2015-03-31
申请号：US12720089
申请日：2010-03-09
申请人： Hiroki Ohara , Toshinari Sasaki
发明人： Hiroki Ohara , Toshinari Sasaki
IPC分类号： H01L21/84 , C01G51/00 , H01L29/786 , C01G45/00 , H01L27/12 , H01L29/66 , C01G15/00 , C01G53/00 , C01G49/00 , H01L21/02
CPC分类号： H01L29/66969 , C01G15/006 , C01G45/006 , C01G49/009 , C01G51/006 , C01G53/006 , C01P2002/52 , C01P2006/40 , H01L21/02164 , H01L21/02178 , H01L21/02183 , H01L21/02266 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/441 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/7869
摘要： An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present invention includes the steps of: forming a first conductive layer which functions as a gate electrode over a substrate; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer over the first insulating layer so that part of the semiconductor layer overlaps with the first conductive layer; forming a second conductive layer to be electrically connected to the semiconductor layer; forming a second insulating layer to cover the semiconductor layer and the second conductive layer; forming a third conductive layer to be electrically connected to the second conductive layer; performing first heat treatment after forming the semiconductor layer and before forming the second insulating layer; and performing second heat treatment after forming the second insulating layer.
摘要翻译：目的是提供一种具有有利特性的半导体元件的半导体器件。本发明的制造方法包括以下步骤：在衬底上形成用作栅电极的第一导电层; 形成第一绝缘层以覆盖所述第一导电层; 在所述第一绝缘层上形成半导体层，使得所述半导体层的一部分与所述第一导电层重叠; 形成与半导体层电连接的第二导电层; 形成覆盖半导体层和第二导电层的第二绝缘层; 形成与第二导电层电连接的第三导电层; 在形成半导体层之后并在形成第二绝缘层之前进行第一热处理; 以及在形成所述第二绝缘层之后进行第二热处理。

42. 发明授权

US08890150B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08890150B2
公开(公告)日：2014-11-18
申请号：US13353608
申请日：2012-01-19
申请人： Toshinari Sasaki , Kosei Noda , Yuta Endo
发明人： Toshinari Sasaki , Kosei Noda , Yuta Endo
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/045 , H01L29/24 , H01L29/247 , H01L29/7869 , H01L29/78693
摘要： A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. A p-type oxide semiconductor material is contained in an n-type oxide semiconductor film, whereby carriers which are generated in the oxide semiconductor film without intention can be reduced. This is because electrons generated in the n-type oxide semiconductor film without intention are recombined with holes generated in the p-type oxide semiconductor material to disappear. Accordingly, it is possible to reduce carriers which are generated in the oxide semiconductor film without intention.
摘要翻译：通过对使用氧化物半导体膜的晶体管赋予稳定的电特性来制造高可靠性的半导体器件。 p型氧化物半导体材料包含在n型氧化物半导体膜中，由此可以减少在氧化物半导体膜中产生的载流子。这是因为在n型氧化物半导体膜中产生的电子没有意图与在p型氧化物半导体材料中产生的空穴重新组合而消失。因此，可以无意地减少在氧化物半导体膜中产生的载流子。

43. 发明授权

US08847233B2 Semiconductor device having a trenched insulating layer coated with an oxide semiconductor film 有权
标题翻译：具有涂覆有氧化物半导体膜的沟槽绝缘层的半导体器件
公开(公告)号：US08847233B2
公开(公告)日：2014-09-30
申请号：US13463092
申请日：2012-05-03
申请人： Atsuo Isobe , Toshinari Sasaki , Junichi Koezuka , Shunpei Yamazaki
发明人： Atsuo Isobe , Toshinari Sasaki , Junichi Koezuka , Shunpei Yamazaki
IPC分类号： H01L29/04 , H01L29/10 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/108 , H01L21/84 , H01L49/02 , H01L21/425 , H01L29/66 , H01L29/786 , H01L27/115
CPC分类号： H01L29/4238 , H01L21/02565 , H01L21/265 , H01L21/425 , H01L21/84 , H01L27/1085 , H01L27/10876 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L28/40 , H01L29/045 , H01L29/0847 , H01L29/66477 , H01L29/66742 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L29/78693
摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
摘要翻译：本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。利用上述结构，可以实现小型化。此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

44. 发明授权

US08822989B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08822989B2
公开(公告)日：2014-09-02
申请号：US13613178
申请日：2012-09-13
申请人： Shunpei Yamazaki , Atsuo Isobe , Toshinari Sasaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Toshinari Sasaki
IPC分类号： H01L29/10 , H01L29/786 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/12 , H01L27/1225 , H01L29/10 , H01L29/41733 , H01L29/41775
摘要： Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.
摘要翻译：提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

45. 发明授权

US08809854B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08809854B2
公开(公告)日：2014-08-19
申请号：US13446020
申请日：2012-04-13
申请人： Atsuo Isobe , Toshinari Sasaki
发明人： Atsuo Isobe , Toshinari Sasaki
IPC分类号： H01L29/10
CPC分类号： H01L29/78696 , H01L21/02565 , H01L21/02592 , H01L21/02667 , H01L23/564 , H01L27/1052 , H01L27/1156 , H01L27/1225 , H01L29/045 , H01L29/24 , H01L29/4236 , H01L29/42384 , H01L29/51 , H01L29/66969 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.
摘要翻译：将稳定的电特性和高可靠性提供给包括氧化物半导体的小型化和集成的半导体器件。在包括氧化物半导体膜的晶体管（半导体器件）中，氧化物半导体膜沿着形成在绝缘层中的沟槽（沟槽）设置。沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分，并且氧化物半导体膜设置成与底表面接触，下端拐角部分和沟槽的内壁表面。氧化物半导体膜包括具有基本上垂直于至少在下端拐角部分的表面的c轴的晶体。

46. 发明授权

US08802515B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08802515B2
公开(公告)日：2014-08-12
申请号：US13289436
申请日：2011-11-04
申请人： Yuta Endo , Toshinari Sasaki , Kosei Noda
发明人： Yuta Endo , Toshinari Sasaki , Kosei Noda
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/02 , H01L21/02112 , H01L21/02403 , H01L21/28 , H01L21/425 , H01L21/477 , H01L29/42384 , H01L29/518 , H01L29/78618 , H01L29/7869
摘要： A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
摘要翻译：使用其中氧化物半导体包括在沟道区域中的晶体管制造半导体器件，并且不太可能引起由于短沟道效应引起的电特性的变化。半导体器件包括具有一对氧氮化物半导体区域的氧化物半导体膜，该氧氮化物半导体区域包括氮和夹在一对氧氮化物半导体区域之间的氧化物半导体区域，栅极绝缘膜和设置在氧化物半导体区域上的栅电极，栅极绝缘胶片位于其间。这里，一对氧氮化物半导体区域用作晶体管的源极区域和漏极区域，氧化物半导体区域用作晶体管的沟道区域。

47. 发明授权

US08546180B2 Method for manufacturing oxide semiconductor device 有权
标题翻译：氧化物半导体器件的制造方法
公开(公告)号：US08546180B2
公开(公告)日：2013-10-01
申请号：US12846534
申请日：2010-07-29
申请人： Shunpei Yamazaki , Hiroki Ohara , Toshinari Sasaki , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Hiroki Ohara , Toshinari Sasaki , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L21/00
CPC分类号： H01L27/1225 , G02F1/133345 , G02F1/1337 , G02F1/134309 , G02F1/136227 , G02F1/136277 , G02F1/1368 , H01L27/1214 , H01L27/124 , H01L27/1248 , H01L29/24 , H01L29/517 , H01L29/78609 , H01L29/7869
摘要： An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
摘要翻译：目的在于提供一种半导体器件，其具有可以充分降低布线之间的寄生电容的结构。用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上。在与氧化物绝缘层的形成相同的步骤中，形成覆盖氧化物半导体层的周边部分的氧化物绝缘层。设置覆盖氧化物半导体层的周边部分的氧化物绝缘层以增加栅极电极层与形成在栅电极层的上方或周围的布线层之间的距离，从而降低寄生电容。

48. 发明授权

US08519387B2 Semiconductor device and method for manufacturing 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08519387B2
公开(公告)日：2013-08-27
申请号：US13185779
申请日：2011-07-19
申请人： Yuta Endo , Kosei Noda , Toshinari Sasaki
发明人： Yuta Endo , Kosei Noda , Toshinari Sasaki
IPC分类号： H01L29/10
CPC分类号： H01L29/66969 , H01L21/02164 , H01L21/02367 , H01L21/02565 , H01L21/02631 , H01L29/66742 , H01L29/78603 , H01L29/78618 , H01L29/7869
摘要： An insulating layer which releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer which releases a small amount of oxygen is used as an insulating layer in contact with a source region and a drain region of the oxide semiconductor layer. By releasing oxygen from the insulating layer which releases a large amount of oxygen, oxygen deficiency in the channel region and an interface state density between the insulating layer and the channel region can be reduced, so that a highly reliable semiconductor device having small variation in electrical characteristics can be manufactured. The source region and the drain region are provided in contact with the insulating layer which releases a small amount of oxygen, thereby suppressing the increase of the resistance of the source region and the drain region.
摘要翻译：使用释放大量氧的绝缘层作为与氧化物半导体层的沟道区域接触的绝缘层，并且使用释放少量氧的绝缘层作为与源极接触的绝缘层区域和氧化物半导体层的漏极区域。通过从释放大量氧的绝缘层释放氧气，可以减少沟道区域中的氧缺乏以及绝缘层和沟道区域之间的界面态密度，从而可以降低电子变化小的高度可靠的半导体器件特性可以制造。源极区域和漏极区域设置成与释放少量氧气的绝缘层接触，从而抑制源极区域和漏极区域的电阻的增加。

49. 发明授权

US08426868B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08426868B2
公开(公告)日：2013-04-23
申请号：US12604622
申请日：2009-10-23
申请人： Kengo Akimoto , Toshinari Sasaki
发明人： Kengo Akimoto , Toshinari Sasaki
IPC分类号： H01L21/02
CPC分类号： H01L29/7869 , G02F1/1368 , G02F1/167 , H01L27/1225 , H01L27/1248 , H01L27/1259 , H01L27/127 , H01L27/3262 , H01L29/04 , H01L29/24 , H01L29/42356 , H01L29/45 , H01L29/66742 , H01L29/66969 , H01L29/78618 , H01L29/78693 , H01L29/78696
摘要： An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
摘要翻译：目的是提高使用氧化物半导体的薄膜晶体管的场效应迁移率。另一个目的是抑制即使在具有改善的场效应迁移率的薄膜晶体管中，关断电流的增加。在使用氧化物半导体层的薄膜晶体管中，通过形成具有比氧化物半导体层和栅极绝缘层之间的氧化物半导体层更高的导电性和更小的厚度的半导体层，薄膜晶体管的场效应迁移率可以是可以抑制切断电流的提高。

50. 发明授权

US08318551B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08318551B2
公开(公告)日：2012-11-27
申请号：US12627204
申请日：2009-11-30
申请人： Kengo Akimoto , Toshinari Sasaki
发明人： Kengo Akimoto , Toshinari Sasaki
IPC分类号： H01L21/84 , H01L29/10 , H01L29/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/41733 , H01L29/66969
摘要： A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second drain electrode layer over the oxide semiconductor layer. A first part, a second part, and a third part of a bottom surface are in contact with the first source electrode layer, the first drain electrode layer, and the gate insulating layer respectively. A first part and a second part of the top surface are in contact with the second source electrode layer and the second drain electrode layer respectively. The first source electrode layer and the first drain electrode layer are electrically connected to the second source electrode layer and the second drain electrode layer respectively.
摘要翻译：衬底上的栅电极层; 栅电极层上的栅极绝缘层; 栅极绝缘层上的第一源极电极层和第一漏极电极层; 栅极绝缘层上的氧化物半导体层; 以及在所述氧化物半导体层上的第二源极电极层和第二漏极电极层。第一部分，第二部分和底部表面的第三部分分别与第一源极电极层，第一漏极电极层和栅极绝缘层接触。上表面的第一部分和第二部分分别与第二源极电极层和第二漏极电极层接触。第一源极电极层和第一漏极电极层分别与第二源极电极层和第二漏极电极层电连接。

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