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41. 发明授权

US09330913B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09330913B2
公开(公告)日：2016-05-03
申请号：US12912744
申请日：2010-10-27
申请人： Jang-Hyun You , Jong-Min Lee , Dong-Hwa Kwak , Tae-Yong Kim , Jong-Hoon Na , Young-Woo Park , Dong-Sik Lee , Jee-Hoon Han
发明人： Jang-Hyun You , Jong-Min Lee , Dong-Hwa Kwak , Tae-Yong Kim , Jong-Hoon Na , Young-Woo Park , Dong-Sik Lee , Jee-Hoon Han
IPC分类号： H01L29/40 , H01L21/033 , H01L21/28 , H01L21/308 , H01L21/3213 , H01L21/762 , H01L27/115 , H01L29/66
CPC分类号： H01L21/0337 , H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L27/11521 , H01L27/11536 , H01L29/66825
摘要： A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.
摘要翻译：半导体器件包括第一，第二和第三导线，每个导线具有形成在衬底上并且沿第一方向延伸的相应的线部分，并且具有相应的分支部分，该分支部分从相应线部分的端部沿与第一个方向中间导线的分支部分设置在外导电线的相应分支部分之间并且短于接触焊盘可以与导电线的这种分支部分一体形成。

42. 发明授权

US08748286B2 Method of fabricating a nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08748286B2
公开(公告)日：2014-06-10
申请号：US13198157
申请日：2011-08-04
申请人： Jong-Hoon Na , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
发明人： Jong-Hoon Na , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11 , H01L27/11519 , H01L27/11524
摘要： A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
摘要翻译：一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽，所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

43. 发明授权

US08729615B2 Non-volatile memory device with high speed operation and lower power consumption 有权
标题翻译：具有高速运行，功耗低的非易失性存储器件
公开(公告)号：US08729615B2
公开(公告)日：2014-05-20
申请号：US13248333
申请日：2011-09-29
申请人： Chang Hyun Lee , Young-Woo Park , Kye-Hyun Kyung , Cheon-An Lee , Sung-il Chang , Chul Bum Kim
发明人： Chang Hyun Lee , Young-Woo Park , Kye-Hyun Kyung , Cheon-An Lee , Sung-il Chang , Chul Bum Kim
IPC分类号： H01L27/108
CPC分类号： H01L21/823857 , G11C16/0483 , G11C16/30 , H01L27/105 , H01L27/11546 , H01L27/11556
摘要： A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.
摘要翻译：半导体存储器件具有存储单元区域和周边区域。该器件包括具有不同厚度的栅极绝缘膜的外围区域的低电压晶体管。例如，在存储器件的输入/输出电路中使用的低电压晶体管的栅极绝缘膜可以比用于存储器件的核心电路中的低电压晶体管的栅极绝缘膜更薄。由于在输入/输出电路中使用的低压晶体管形成为与核心电路或高压泵浦电路所使用的低压晶体管不同，所以可以是非易失性存储器件的高速工作和低功耗特性。

44. 发明申请

US20120202335A1 METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES 有权
标题翻译：制造非活性存储器件的方法，包括有源区域和相关器件之间的失调
公开(公告)号：US20120202335A1
公开(公告)日：2012-08-09
申请号：US13300787
申请日：2011-11-21
申请人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
发明人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/764
摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
摘要翻译：制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。沟槽和其间的有源区延伸到衬底的第一和第二器件区域。牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区在第二设备区域中。还讨论了相关的方法和设备。

45. 发明申请

US20120146118A1 NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION 有权
标题翻译：具有高速运行和低功耗的非易失性存储器件
公开(公告)号：US20120146118A1
公开(公告)日：2012-06-14
申请号：US13248333
申请日：2011-09-29
申请人： Chang-Hyun Lee , Young-Woo Park , Kye-Hyun Kyung , Cheon-An Lee , Sung-il Chang , Chul Bum Kim
发明人： Chang-Hyun Lee , Young-Woo Park , Kye-Hyun Kyung , Cheon-An Lee , Sung-il Chang , Chul Bum Kim
IPC分类号： H01L27/108 , H01L27/092
CPC分类号： H01L21/823857 , G11C16/0483 , G11C16/30 , H01L27/105 , H01L27/11546 , H01L27/11556
摘要： A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.
摘要翻译：半导体存储器件具有存储单元区域和周边区域。该器件包括具有不同厚度的栅极绝缘膜的外围区域的低电压晶体管。例如，在存储器件的输入/输出电路中使用的低电压晶体管的栅极绝缘膜可以比用于存储器件的核心电路中的低电压晶体管的栅极绝缘膜更薄。由于在输入/输出电路中使用的低压晶体管形成为与核心电路或高压泵浦电路所使用的低压晶体管不同，所以可以是非易失性存储器件的高速工作和低功耗特性。

46. 发明授权

US07106522B2 Zoom lens 有权
标题翻译：变焦镜头
公开(公告)号：US07106522B2
公开(公告)日：2006-09-12
申请号：US10989591
申请日：2004-11-16
申请人： Young-Woo Park
发明人： Young-Woo Park
IPC分类号： G02B15/177
CPC分类号： G02B15/177
摘要： The present invention is directed to a zoom lens which includes, in order from an object side: a first lens group having a negative refractive power; a second lens group having a positive refractive power; and a third lens group having a positive refractive power. While zooming from a wide-angle position to a telephoto position, the distance between the third lens group and an image side is greater at the wide-angle position than at the telephoto position. The zoom lens satisfies the following conditional expression: 1.0 ≤ L II f W ⁢ f T ≤ 1.5 where fW denotes the total focal length at the wide-angle position; fT denotes the total focal length at the telephoto position; and LII denotes the moving distance of the second lens group from the wide-angle position to the telephoto position.
摘要翻译：本发明涉及一种变焦透镜，其从物体侧依次包括具有负屈光力的第一透镜组; 具有正屈光力的第二透镜组; 以及具有正屈光力的第三透镜组。当从广角位置变焦到远摄位置时，第三透镜组和像侧之间的距离在广角位置比在远摄位置处更大。变焦镜头满足以下条件表达式： $1.0<=\sqrt{表示在宽范围内的总焦距，角度位置 f表示在远摄位置的总焦距; L II表示第二透镜组从广角位置到远摄位置的移动距离。}$

47. 发明授权

US06853498B2 Zoom lens 有权
标题翻译：变焦镜头
公开(公告)号：US06853498B2
公开(公告)日：2005-02-08
申请号：US10853669
申请日：2004-05-25
申请人： Sung-Woo Kim , Young-Woo Park
发明人： Sung-Woo Kim , Young-Woo Park
IPC分类号： G02B13/18 , G02B15/177 , G02B15/14
CPC分类号： G02B13/18 , G02B15/177
摘要： The zoom lens comprises, in order from an object side: a first lens group having a negative refractive power, the first lens group including a first lens having a negative refractive power, and a second lens having a positive refractive power; a second lens group having a positive refractive power, the second lens group including a third lens having a positive refractive power, and a fourth lens having a negative refractive power; and a third lens group having a positive refractive power, the third lens group including a fifth lens having a positive refractive power, the zoom lens satisfying the following conditional expression: - 3.0
摘要翻译：变焦透镜从物体侧依次包括具有负屈光力的第一透镜组，第一透镜组包括具有负折光力的第一透镜和具有正折光力的第二透镜; 具有正屈光力的第二透镜组，所述第二透镜组包括具有正折光力的第三透镜和具有负屈光力的第四透镜; 和具有正折光力的第三透镜组，所述第三透镜组包括具有正折光力的第五透镜，所述变焦透镜满足以下条件表达式：其中f1表示第一透镜组的焦距; fw表示广角位置处的总焦距。

48. 发明授权

US06511919B1 Contacts for a bit line and a storage node in a semiconductor device 有权
标题翻译：半导体器件中的位线和存储节点的触点
公开(公告)号：US06511919B1
公开(公告)日：2003-01-28
申请号：US09649386
申请日：2000-08-28
申请人： Young-Woo Park , Won-Sung Lee
发明人： Young-Woo Park , Won-Sung Lee
IPC分类号： H01L21461
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/0207 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.
摘要翻译：在氧化物层中形成自对准接触孔以在相邻栅极线之间露出半导体衬底的方法。栅极线形成为使得存储节点接触区域中的相邻栅极线之间的间隔等于或大于位线接触区域中的相邻栅极线之间的间隔。绝缘层沉积在栅极线上以填充栅极线之间的空间。使用光刻工艺在绝缘层中形成自对准的接触孔。结果，可以避免存储节点接触孔不开现象和位线接触肩部过蚀刻现象。

49. 发明授权

US06239022B1 Method of fabricating a contact in a semiconductor device 有权
标题翻译：在半导体器件中制造接触的方法
公开(公告)号：US06239022B1
公开(公告)日：2001-05-29
申请号：US09604708
申请日：2000-06-27
申请人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
发明人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/31116 , H01L21/32137 , H01L21/7684
摘要： A method for forming a contact plug formed of polysilicon and a method for manufacturing a semiconductor device using the same are provided. The contact plug is formed by etching back polysilicon which fills a contact hole and is deposited on an interlayer dielectric film using a gas mixture of SF6, CHF3, and CF4, thus planarizing the polysilicon. Also, the contact plug can be made protrude above the interlayer dielectric film by etching the entire surface of the exposed interlayer dielectric film around the polysilicon contact plug formed by etching back the polysilicon. According to the present invention, the degree of planarization of the polysilicon contact plug is improved by etching back the polysilicon using the gas mixture of SF6, CHF3, and CF4. Furthermore, it is possible to prevent contact failure due to the depression of the contact plug by etching the entire surface of the interlayer dielectric film thus causing the contact plug to protrude above the interlayer dielectric film, thereby increasing the plug's contact area and reducing the contact failure.
摘要翻译：提供一种用于形成由多晶硅形成的接触插塞的方法以及使用其形成半导体器件的方法。接触插塞是通过将填充接触孔的多晶硅蚀刻回来形成的，并且使用SF6，CHF3和CF4的气体混合物沉积在层间电介质膜上，从而平坦化多晶硅。此外，通过蚀刻暴露的层间电介质膜的整个表面，接触插塞可以突出在层间电介质膜的上方，通过蚀刻多晶硅而形成的多晶硅接触插塞周围。根据本发明，通过使用SF6，CHF3和CF4的气体混合物蚀刻多晶硅来提高多晶硅接触插塞的平坦化程度。此外，可以通过蚀刻层间电介质膜的整个表面来防止接触插塞的接触故障，从而使接触插塞突出到层间电介质膜之上，从而增加插头的接触面积并减少接触失败。

50. 发明授权

US06171926B2 Methods for fabricating integrated circuit capacitor electrodes using first and second insulating layers and a buffer layer 有权
标题翻译：使用第一和第二绝缘层和缓冲层制造集成电路电容器电极的方法
公开(公告)号：US06171926B2
公开(公告)日：2001-01-09
申请号：US09289364
申请日：1999-04-09
申请人： Kwang-Youl Chun , Young-Woo Park , Yong-Jin Kim
发明人： Kwang-Youl Chun , Young-Woo Park , Yong-Jin Kim
IPC分类号： H01L2120
CPC分类号： H01L28/92 , H01L27/10814 , H01L28/60 , H01L28/84
摘要： Integrated circuit capacitor lower electrodes are fabricated by forming a plurality of spaced-apart contact pads on an integrated circuit substrate. A first insulating layer is formed on the integrated circuit substrate including on the contact pads. A plurality of spaced-apart conductive lines is formed on the first insulating layer that are laterally offset from the plurality of spaced-apart contact pads. A second insulating layer is formed on the first insulating layer including on the conductive lines. A buffer layer comprising material that is different from the second insulating layer, is formed on the second insulating layer. Openings are formed that extend through the buffer layer, through the second insulating layer and into the first insulating layer between the conductive lines to expose the contact pads. A conductive layer is formed in the openings and on the buffer layer. The conductive layer is etched between the openings to form the capacitor lower electrodes. The buffer layer preferably comprises material that has lower reflectivity than that of the second insulating layer and also preferably comprises material that has an etch rate for a predetermined etchant, that is intermediate that of the second insulating layer and the conductive layer. The first and second insulating layers preferably comprise silicon dioxide, the buffer layer preferably comprises at least one of silicon nitride and silicon oxynitride and the conductive layer preferably comprises polysilicon. During etching, a polymer preferably is formed on the capacitor lower electrode sidewalls adjacent the buffer layer. The etchant preferably is a plasma etchant including sulfur hexafluoride, chlorine and/or nitrogen gases.
摘要翻译：集成电路电容器下电极通过在集成电路基板上形成多个间隔开的接触焊盘来制造。在包括接触焊盘的集成电路基板上形成第一绝缘层。在第一绝缘层上形成多个间隔开的导电线，其横向偏离多个间隔开的接触焊盘。在包括导电线的第一绝缘层上形成第二绝缘层。包含与第二绝缘层不同的材料的缓冲层形成在第二绝缘层上。形成开口，其延伸穿过缓冲层，穿过第二绝缘层并进入导线之间的第一绝缘层，以露出接触焊盘。在开口和缓冲层上形成导电层。在开口之间蚀刻导电层以形成电容器下电极。缓冲层优选地包括具有比第二绝缘层低的反射率的材料，并且还优选地包括具有预定蚀刻剂的蚀刻速率的材料，其与第二绝缘层和导电层的蚀刻速率相等。第一绝缘层和第二绝缘层优选地包括二氧化硅，缓冲层优选地包括氮化硅和氮氧化硅中的至少一种，并且导电层优选地包括多晶硅。在蚀刻期间，优选在与缓冲层相邻的电容器下电极侧壁上形成聚合物。蚀刻剂优选是等离子体蚀刻剂，包括六氟化硫，氯和/或氮气。

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