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41. 发明授权

US07439176B2 Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method 有权
标题翻译：半导体器件多层结构，其制造方法，具有该半导体器件的半导体器件的半导体器件制造方法
公开(公告)号：US07439176B2
公开(公告)日：2008-10-21
申请号：US11379350
申请日：2006-04-19
申请人： Jae-Hwa Park , Jang-Hee Lee , Dae-Yong Kim , Hee-Sook Park
发明人： Jae-Hwa Park , Jang-Hee Lee , Dae-Yong Kim , Hee-Sook Park
IPC分类号： H01L21/44 , H01L23/52
CPC分类号： H01L21/823842 , H01L21/823828 , H01L21/823835
摘要： In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. After forming the diffusion barrier layer, a heat treatment process may be additionally performed thereon. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.
摘要翻译：在一个实施例中，半导体器件包括形成在半导体衬底上的半导体衬底和掺杂导电层。在掺杂导电层上方形成扩散阻挡层。扩散阻挡层包括非晶半导体材料。在形成扩散阻挡层之后，还可以在其上进行热处理工艺。在扩散阻挡层上形成欧姆接触层。金属阻挡层形成在欧姆接触层上。在金属阻挡层上形成金属层。

42. 发明申请

US20070195609A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20070195609A1
公开(公告)日：2007-08-23
申请号：US11653866
申请日：2007-01-17
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

43. 发明授权

US06284605B1 Method for fabricating semiconductor power integrated circuit 有权
标题翻译：制造半导体功率集成电路的方法
公开(公告)号：US06284605B1
公开(公告)日：2001-09-04
申请号：US09428403
申请日：1999-10-28
申请人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
发明人： Jong-Dae Kim , Sang-Gi Kim , Jin-Gun Koo , Dae-Yong Kim
IPC分类号： H01L21336
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
摘要翻译：一种制造半导体功率集成电路的方法包括以下步骤：形成具有至少一个有源区的半导体结构，其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区，形成用于有源区的隔离，其中沟槽具有来自半导体结构的表面的预定深度，在沟槽内部和半导体结构之上形成第一TEOS氧化物层，其中第一TEOS氧化物层具有来自该半导体结构的预定厚度在所述第一TEOS氧化物层上形成第二TEOS氧化物层，其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度，并且对所述第一TEOS氧化物层进行选择性蚀刻第一和第二TEOS氧化物层，从而同时形成场氧化物层图案，二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。

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