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41. 发明申请

US20130193483A1 Mosfet Structures Having Compressively Strained Silicon Channel 审中-公开
标题翻译：具有压缩应变硅通道的Mosfet结构
公开(公告)号：US20130193483A1
公开(公告)日：2013-08-01
申请号：US13359858
申请日：2012-01-27
申请人： Stephen W. Bedell , Kangguo Cheng , Bahman Hekmatshoartabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Kangguo Cheng , Bahman Hekmatshoartabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/41783 , H01L29/7848
摘要： MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.
摘要翻译：提供具有压缩应变硅通道的MOSFET结构。提供一种半导体器件，其包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构，其中所述场效应晶体管结构包括形成在所述栅极堆叠下方的沟道; 以及在所述硅衬底的至少一部分上的压缩应变硅层，以压缩所述通道。

42. 发明申请

US20130040438A1 EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
标题翻译：首先使用HCl / GeH4 / H2SiCl2表面清洁的外延工艺
公开(公告)号：US20130040438A1
公开(公告)日：2013-02-14
申请号：US13206248
申请日：2011-08-09
申请人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
发明人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
IPC分类号： H01L21/205 , H01L21/322
CPC分类号： H01L21/0237 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661
摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
摘要翻译：一种沉积外延层的方法，包括化学清洗半导体衬底的沉积表面，并在预烘烤温度下用含氢气体处理半导体衬底的沉积表面。含氢气体处理可以在外延沉积室中进行。含氢气体从半导体衬底的沉积表面去除含氧材料。然后可以用包含至少一种盐酸（HCl），锗烷（GeH4）和二氯硅烷（H 2 SiCl 2））的气流来处理半导体衬底的沉积表面，该气流随着温度从预烘烤温度达到外延沉积温度。可以将至少一种源气体施加到沉积表面，用于材料层的外延沉积。

43. 发明授权

US08354694B2 CMOS transistors with stressed high mobility channels 有权
标题翻译：具有应力高移动性通道的CMOS晶体管
公开(公告)号：US08354694B2
公开(公告)日：2013-01-15
申请号：US12855738
申请日：2010-08-13
申请人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.
摘要翻译：形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域。在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成，使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

44. 发明申请

US20120305940A1 Defect Free Si:C Epitaxial Growth 审中-公开
标题翻译：缺陷Si：C外延生长
公开(公告)号：US20120305940A1
公开(公告)日：2012-12-06
申请号：US13151238
申请日：2011-06-01
申请人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
发明人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L29/045 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.
摘要翻译：公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。接受具有{100}晶体取向的主表面的晶片。以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

45. 发明申请

US20120210932A1 LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION 有权
标题翻译：低温选择性外延生长用于器件集成的硅
公开(公告)号：US20120210932A1
公开(公告)日：2012-08-23
申请号：US13032866
申请日：2011-02-23
申请人： BAHMAN HEKMATSHOAR-TABARI , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： BAHMAN HEKMATSHOAR-TABARI , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： C30B25/02 , C30B25/10
CPC分类号： C30B25/04 , C30B25/105 , C30B25/14 , C30B25/183 , C30B25/186 , C30B29/06 , C30B33/12 , H01L21/02381 , H01L21/02395 , H01L21/02532 , H01L21/02576 , H01L21/02584 , H01L21/0262 , H01L21/02639 , H01L21/3065
摘要： An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
摘要翻译：外延生长方法包括提供衬底材料的暴露的结晶区域。硅在低温工艺中外延沉积在衬底材料上，其中沉积温度低于500摄氏度。源气体用稀释气体稀释，稀释气体与原料气体的气体比小于1000。

46. 发明授权

US07691688B2 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07691688B2
公开(公告)日：2010-04-06
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

47. 发明授权

US07402466B2 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07402466B2
公开(公告)日：2008-07-22
申请号：US11492271
申请日：2006-07-25
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

48. 发明授权

US07087965B2 Strained silicon CMOS on hybrid crystal orientations 失效
公开(公告)号：US07087965B2
公开(公告)日：2006-08-08
申请号：US10830347
申请日：2004-04-22
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

49. 发明授权

US07084460B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
公开(公告)号：US07084460B2
公开(公告)日：2006-08-01
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/12 , H01L31/036 , H01L71/01 , H01L71/12 , H01L31/039
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

50. 发明授权

US10011920B2 Low-temperature selective epitaxial growth of silicon for device integration 有权
公开(公告)号：US10011920B2
公开(公告)日：2018-07-03
申请号：US13032866
申请日：2011-02-23
申请人： Bahman Hekmatshoar-Tabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoar-Tabari , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： C30B25/04 , C30B25/10 , C30B25/14 , C30B29/06 , C30B25/18 , C30B33/12 , H01L21/02 , H01L21/3065
CPC分类号： C30B25/04 , C30B25/105 , C30B25/14 , C30B25/183 , C30B25/186 , C30B29/06 , C30B33/12 , H01L21/02381 , H01L21/02395 , H01L21/02532 , H01L21/02576 , H01L21/02584 , H01L21/0262 , H01L21/02639 , H01L21/3065
摘要： An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

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