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41. 发明授权

US06288421B1 Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8″ wafer 失效
标题翻译：半导体存储器电路包括用于8“晶圆中的16M至17M存储单元的裸片位置
公开(公告)号：US06288421B1
公开(公告)日：2001-09-11
申请号：US08929585
申请日：1997-09-15
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27108
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6 inch, 8 inch and 12 inch wafers for 4 M, 16 M, 64 M and 256 M integration levels. Further, a semiconductor memory device includes, i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于6M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

42. 发明授权

US6163490A Semiconductor memory remapping 有权
标题翻译：半导体存储器重映射
公开(公告)号：US6163490A
公开(公告)日：2000-12-19
申请号：US401554
申请日：1999-09-22
申请人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
发明人： James M. Shaffer , Brent Keeth , Eugene H. Cloud , Salman Akram
IPC分类号： G11C7/00
摘要： Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.
摘要翻译：通过将存储器的逻辑地址空间划分成多个地址部分，将有缺陷的存储器编程为具有连续的地址空间。识别包含映射到有缺陷的存储器位置的地址的地址部分。最初映射到所识别的地址部分中的地址的物理存储器位置被重新映射到地址空间一端的地址段中的地址。结束地址部分中的地址被禁用。或者，提供备用存储器，并将结束地址部分中的地址重新映射到备用存储器中的物理位置。应用类似的重新映射程序来修复存储器中的有缺陷的数据路径。重映射过程适用于存储器或存储器模块。

43. 发明授权

US6115318A Clock vernier adjustment 失效
公开(公告)号：US6115318A
公开(公告)日：2000-09-05
申请号：US759351
申请日：1996-12-03
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C11/401 , G06F12/00 , G06F13/42 , G11C7/10 , G11C7/22 , G11C8/06 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C8/06
摘要： A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.

44. 发明授权

US6111446A Integrated circuit data latch driver circuit 失效
标题翻译：集成电路数据锁存驱动电路
公开(公告)号：US6111446A
公开(公告)日：2000-08-29
申请号：US45609
申请日：1998-03-20
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C7/10 , H03K5/15 , H03K5/151 , H03K5/13
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069 , G11C7/1078 , H03K5/15066 , H03K5/1515
摘要： A synchronous memory device and system are described which communicates bi-directional data via a bus and data clock. To capture data from the bus, a memory device latch circuit is described which operates in response to internally generated clock signals. A pulse generator circuit is described which produces these internal clock signals, and insures accurate latching of data by minimizing signal skew between the internal clock signals to avoid wasting valuable timing. The pulse generator circuit has at least two propagation paths that are symmetrical and operate in response to clock signals which are 90 degrees out-of-phase. A second pulse generator circuit is described minimizes skew by having symmetrical clock paths and also corrects duty cycle error present on the data clock. This second circuit uses three clock signals which have relative phases of 0, 90 and 180 degrees.
摘要翻译：描述了经由总线和数据时钟传送双向数据的同步存储器件和系统。为了从总线捕获数据，描述了响应于内部产生的时钟信号而工作的存储器件锁存电路。描述了产生这些内部时钟信号的脉冲发生器电路，并且通过使内部时钟信号之间的信号偏移最小化来确保数据的精确锁存，以避免浪费有价值的定时。脉冲发生器电路具有对称的至少两个传播路径，并响应于90度异相的时钟信号而工作。描述了第二脉冲发生器电路通过具有对称时钟路径使偏移最小化，并且还校正存在于数据时钟上的占空比误差。该第二电路使用三个时钟信号，其相位相位为0,90和180度。

45. 发明授权

US6069510A Low-skew differential signal converter 有权
标题翻译：低偏差差分信号转换器
公开(公告)号：US6069510A
公开(公告)日：2000-05-30
申请号：US200250
申请日：1998-11-25
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： H03K5/151 , H03K17/00
CPC分类号： H03K5/151
摘要： A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.
摘要翻译：低偏移单端到差分信号转换器包括驱动一对输出驱动器电路的常规单端到差分转换器。每个驱动电路由分别接收电源电压或参考电压的一对传输门形成。响应于来自常规转换器的反相信号，传输门仅传送电源或参考电压的一部分。转移电压的部分不足以触发输出驱动器中的输出元件，并且来自驱动器的输出电压不响应于非反相信号而转变。反相信号使传输门的输出完全转变，触发相应的输出反相器。因为反相信号引起两个输出信号的转变，所以输出信号的偏斜相对于反相和非反相信号的偏斜减小。

46. 发明授权

US6043562A Digit line architecture for dynamic memory 失效
标题翻译：动态内存的数字线结构
公开(公告)号：US6043562A
公开(公告)日：2000-03-28
申请号：US701749
申请日：1996-08-22
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C7/18 , G11C11/4097 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/10891 , G11C11/4097 , G11C7/18
摘要： A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F.sup.2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
摘要翻译：描述了一种新颖的双层DRAM架构，其在保持传统折叠架构的噪声性能的同时实现了裸片尺寸的显着降低。芯片尺寸的减小主要是通过使用6个F2或更小的存储单元构建存储器阵列，形成一种交叉点存储单元布局。存储器阵列利用堆叠数字线和垂直数字线扭转来实现折叠架构操作和噪声性能。

47. 发明授权

US6026051A Low skew differential receiver with disable feature 有权
标题翻译：低偏差差分接收器具有禁用功能
公开(公告)号：US6026051A
公开(公告)日：2000-02-15
申请号：US275690
申请日：1999-03-24
申请人： Brent Keeth , Russel J. Baker
发明人： Brent Keeth , Russel J. Baker
IPC分类号： G11C7/00 , G11C8/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018528 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , H03K19/00384
摘要： A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock recciver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.
摘要翻译：用于SynchLink型同步动态随机存取存储器（SLDRAM）的差分时钟接收器包括具有用于偏置其NMOS和PMOS电流源的新颖方法的差分放大器。由差分放大器接收和放大的差分时钟切换一组多路复用器，其通过输出差分输出时钟来响应。多路复用器可以通过无效使能信号“禁用”，因此它们为差分输出时钟输出一个恒定的“0”电平。对于SLDRAM中发现的间歇性数据时钟，差分时钟接收器的禁用功能特别有用。此外，差分放大器的电流源的新型偏置方法给时钟接收器非常低的偏移。

48. 发明授权

US5999480A Dynamic random-access memory having a hierarchical data path 有权
标题翻译：具有分层数据路径的动态随机存取存储器
公开(公告)号：US5999480A
公开(公告)日：1999-12-07
申请号：US167259
申请日：1998-10-06
申请人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.
摘要翻译：一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本相同的1M位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

49. 发明授权

US5999033A Low-to-high voltage CMOS driver circuit for driving capacitive loads 有权
标题翻译：用于驱动容性负载的低至高电压CMOS驱动电路
公开(公告)号：US5999033A
公开(公告)日：1999-12-07
申请号：US231853
申请日：1999-01-14
申请人： Brent Keeth , William K. Waller
发明人： Brent Keeth , William K. Waller
IPC分类号： G11C8/08 , H03K3/356 , H03K19/00 , H03K19/0185 , H03L5/00
CPC分类号： G11C8/08 , H03K19/0013 , H03K19/018521 , H03K3/356182
摘要： A high speed, low-to-high voltage CMOS driver circuit has a CMOS output stage, an intermediate voltage translation stage, and an input stage. The input and intermediate stages are designed to generate mutually exclusive control signals which activate the PMOS and NMOS transistors of the output stage. The control signals operably turn "off" the active transistor before turning "on" the inactive transistor. Independent control signals substantially reduce or eliminate crossing current in the output stage to thereby reduce energy power waste.
摘要翻译：高速，低至高电压CMOS驱动电路具有CMOS输出级，中间电压转换级和输入级。输入和中间级被设计为产生激活输出级的PMOS和NMOS晶体管的互斥控制信号。控制信号可操作地在有效晶体管“接通”无效晶体管之前关闭有源晶体管。独立控制信号显着地减少或消除输出级中的交叉电流，从而减少能量浪费。

50. 发明授权

US5901105A Dynamic random access memory having decoding circuitry for partial memory blocks 失效
标题翻译：具有用于部分存储器块的解码电路的动态随机存取存储器
公开(公告)号：US5901105A
公开(公告)日：1999-05-04
申请号：US869035
申请日：1997-06-05
申请人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.
摘要翻译：公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。测试数据压缩电路优化了测试阵列中每个单元的过程。片上拓扑电路简化了器件的测试。

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