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41. 发明申请

US20110210421A1 TRENCH-TYPE CAPACITOR, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR MODULE HAVING THE SEMICONDUCTOR DEVICE 有权
标题翻译： TRENCH型电容器，具有它们的半导体器件和具有半导体器件的半导体器件
公开(公告)号：US20110210421A1
公开(公告)日：2011-09-01
申请号：US13021333
申请日：2011-02-04
申请人： CHUL LEE , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： CHUL LEE , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

42. 发明申请

US20090250736A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090250736A1
公开(公告)日：2009-10-08
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

43. 发明申请

US20080179693A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080179693A1
公开(公告)日：2008-07-31
申请号：US12014370
申请日：2008-01-15
申请人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
发明人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern, and a second impurity region at a surface portion of the second active pattern. The first active pattern extending along a predetermined direction may have a first region and a second region. The second active pattern may have a pillar structure and the conductive layer pattern may include a metal or a metal compound.
摘要翻译：半导体器件包括从衬底突出的第一有源图案，第一有源图案上的第二有源图案，封闭第二有源图案的侧壁的栅极电极，第一有源图案上的导电层图案，第一有源图案上的第一杂质区域第一有源图案和第二有源图案的表面部分处的第二杂质区域。沿着预定方向延伸的第一有源图案可以具有第一区域和第二区域。第二活性图案可以具有柱结构，并且导电层图案可以包括金属或金属化合物。

44. 发明申请

US20070290258A1 FIELD EFFECT TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EXTENDING BENEATH PILLARS 有权
标题翻译：场效应晶体管，包括源/漏区延伸BENEATH PILLARS
公开(公告)号：US20070290258A1
公开(公告)日：2007-12-20
申请号：US11530705
申请日：2006-09-11
申请人： Youngwoong Son , Jae-Man Yoon , Bong-soo Kim , Hyeoungwon Seo
发明人： Youngwoong Son , Jae-Man Yoon , Bong-soo Kim , Hyeoungwon Seo
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/4236 , H01L29/42376 , H01L29/66666 , H01L29/66787 , H01L29/7827
摘要： Field effect transistors include a substrate and a pillar that extends away from the substrate. The pillar includes a base adjacent the substrate, a top remote from the substrate, and a sidewall that extends between the base and the top. An insulated gate is provided on the sidewall. A first source/drain region is provided in the substrate beneath the pillar and adjacent the insulated gate. A second source/drain region that is heavily doped compared to the first source/drain region, is provided in the substrate beneath the pillar and remote from the insulated gate. The pillar may be an I-shaped pillar that is narrower between the base and the top compared to adjacent the base and the top, such that the sidewall includes a recessed portion between the base and the top.
摘要翻译：场效应晶体管包括基板和远离基板延伸的支柱。支柱包括邻近基板的基部，远离基板的顶部以及在基部和顶部之间延伸的侧壁。在侧壁上设置绝缘门。第一源极/漏极区域设置在柱下方的衬底中并且邻近绝缘栅极。与第一源极/漏极区域相比重掺杂的第二源极/漏极区域设置在支柱下方的衬底中并且远离绝缘栅极。支柱可以是与基部和顶部相邻的基部和顶部之间较窄的I形支柱，使得侧壁包括在基部和顶部之间的凹部。

45. 发明授权

US07160780B2 Method of manufacturing a fin field effect transistor 有权
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US07160780B2
公开(公告)日：2007-01-09
申请号：US11066703
申请日：2005-02-23
申请人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
发明人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795
摘要： In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.
摘要翻译：在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。从而，提高了生产效率并提高了设备的性能。翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。此外，可以防止浮体效应或大大降低浮体效应。

46. 发明授权

US08502341B2 Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
标题翻译：沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块
公开(公告)号：US08502341B2
公开(公告)日：2013-08-06
申请号：US13021333
申请日：2011-02-04
申请人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

47. 发明授权

US08247856B2 Semiconductor device including a capacitor electrically connected to a vertical pillar transistor 有权
标题翻译：半导体器件包括电连接到垂直柱晶体管的电容器
公开(公告)号：US08247856B2
公开(公告)日：2012-08-21
申请号：US12728596
申请日：2010-03-22
申请人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/06
CPC分类号： H01L27/10817 , H01L27/10852 , H01L27/10876 , H01L27/10894 , H01L28/91 , H01L29/78
摘要： A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
摘要翻译：半导体器件包括第一晶体管，第二晶体管，绝缘层间图案和电容器。第一晶体管形成在衬底的第一区域中。第一晶体管具有从基板向上突出的柱和设置在柱的上部的杂质区。第二晶体管形成在衬底的第二区域中。绝缘层间图案形成在第一区域和第二区域上以覆盖第二晶体管并暴露柱的上表面。绝缘层间图案具有比第一区域中的柱的上表面大得多的上表面。电容器形成在柱的上部的杂质区上并与杂质区电连接。

48. 发明申请

US20120070950A1 Method of Manufacturing a Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120070950A1
公开(公告)日：2012-03-22
申请号：US13306421
申请日：2011-11-29
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Kang-Uk Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/0847 , H01L21/82385 , H01L21/823885 , H01L27/10823 , H01L27/10894 , H01L27/10897 , H01L29/0692 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure.
摘要翻译：半导体器件包括具有第一区域和第二区域的衬底，设置在第一区域中的第一有源结构，设置在第二区域中的第二有源结构，设置在第一区域中的第一晶体管和设置在第一区域中的第二晶体管第二区。第二活性结构可以具有与第一活性结构的高度基本相同的高度。第一晶体管包括封装第一有源结构的上部的第一栅极结构，形成在第一有源结构的下部的第一杂质区和形成在第一有源结构的上部的第二杂质区。第二晶体管包括形成在第二有源结构上的第二栅极结构和形成在第二有源结构的上部的第三杂质区。

49. 发明申请

US20110183483A1 Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110183483A1
公开(公告)日：2011-07-28
申请号：US13064628
申请日：2011-04-05
申请人： Kang-Uk Kim , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L21/823456
摘要： In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
摘要翻译：在半导体器件中，半导体器件可以包括第一有源结构，第一栅极绝缘层，第一栅极电极，第一杂质区域，第二杂质区域和接触结构。第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。第一栅极绝缘层可以形成在第一上部图案的侧壁上。第一栅电极可以形成在第一栅极绝缘层上。第一杂质区域可以形成在第一下部图案中。第二杂质区域可以形成在第一上部图案中。接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。因此，可以降低接触结构和第二杂质区之间的接触电阻，并且可以提高接触结构的结构稳定性。

50. 发明授权

US07943978B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07943978B2
公开(公告)日：2011-05-17
申请号：US12458262
申请日：2009-07-07
申请人： Kang-Uk Kim , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/823487 , H01L21/823456
摘要： In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
摘要翻译：在半导体器件中，半导体器件可以包括第一有源结构，第一栅极绝缘层，第一栅极电极，第一杂质区域，第二杂质区域和接触结构。第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。第一栅极绝缘层可以形成在第一上部图案的侧壁上。第一栅电极可以形成在第一栅极绝缘层上。第一杂质区域可以形成在第一下部图案中。第二杂质区域可以形成在第一上部图案中。接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。因此，可以降低接触结构和第二杂质区之间的接触电阻，并且可以提高接触结构的结构稳定性。

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