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41. 发明专利

JPH1141178A OPTICAL COMMUNICATION METHOD, OPTICAL REPEATER AND OPTICAL COMMUNICATION SYSTEM 失效
公开(公告)号：JPH1141178A
公开(公告)日：1999-02-12
申请号：JP19699297
申请日：1997-07-23
申请人： HITACHI LTD
发明人： ARITA YUTAKA , NAKAMIGAWA TETSUAKI , KUROSAWA KENICHI , FUKUMARU HIROAKI , OGAWA HISAO
IPC分类号： H04B10/00 , H04B10/07 , H04B10/27 , H04L12/28 , H04L12/46 , H04B10/20 , H04B10/08 , H04B10/24
摘要： PROBLEM TO BE SOLVED: To improve a noise proofing property by partial optical communication in a network by matching driving states of two electric buses connected by an optical fiber with each other. SOLUTION: A bus 20a to connect nodes 30a, 30b is connected with a bus 20b to connect nodes 30c, 30d with optical bus bridge devices 10a, 10b by the optical fiber 50. ON states of the buses 20 (20a, 20b) are observed in a stand-by mode when the bus 20 is not driven by the optical bus bridge devices 10 (10a, 10b). When the bus 20a is changed to the ON state by being driven by the node 30a, the stand-by mode is transferred to an optical output mode and light is outputted from a photoelectric transducer 13a to the optical fiber 50. When the light outputted from the optical fiber 50 is received, the optical bus bridge device 10b is transferred from the stand-by mode to the bus drive mode and the state of the bus 20b is made coincide with that of the bus 20a by performing electric output from a bus driver circuit 11b by the optical bus bridge device 10b. The driving states of the buses 20a, 20b are fetched by the nodes 30b, 30c, 30d.

42. 发明专利

JPH1139253A BUS BRIDGE CIRCUIT AND INFORMATION PROCESSING SYSTEM USING THE CIRCUIT 失效
公开(公告)号：JPH1139253A
公开(公告)日：1999-02-12
申请号：JP19675497
申请日：1997-07-23
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , ARITA YUTAKA , KUROSAWA KENICHI , FUKUMARU HIROAKI , OGAWA HISAO
IPC分类号： G06F13/36 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To accelerate the transmitting speed of an information processing system provided with a plurality of nodes which are connected to each other through buses. SOLUTION: Bus bridge circuits 10 and 20 provided with bus driver circuits for respectively driving buses A and B, photoelectric/electrooptic converters connected to optical fibers, and bus status discriminating circuits which respectively decide the statuses of the bus A and B by receiving signals from the bus driver circuits and the photoelectric/electrooptic converters couple the electric buses A and B with each other through an optical fiber 50 connected with a plurality of nodes 60, 70, 80, and 90.

43. 发明专利

JPH1097462A BIT OPERATION PROCESSOR AND COMPUTER SYSTEM 失效
公开(公告)号：JPH1097462A
公开(公告)日：1998-04-14
申请号：JP24938296
申请日：1996-09-20
申请人： HITACHI LTD
发明人： ARITA YUTAKA , NAKAMIGAWA TETSUAKI , KUROSAWA KENICHI , OKAMOTO TADASHI
IPC分类号： G06F7/38 , G06F7/493 , G06F9/305 , G06F12/02 , G06F15/16 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To fast perform decimal to binary conversion by providing a decimal to binary converter with which an address calculating part converts decimal data into binary data. SOLUTION: A memory address calculating part 105 of a bit operation processor BPU (binary coded decimal) 10 has an operand register 105a and a decimal to binary converter 105b. After the converter 105b converts decimal data of BCD notation which is stored in the register 105a into binary data, the address of data RAM that shows the binary data is accessed by BP-D-ADR (data input signal) 703, and data which sent from the data RAM via BP-D-RDAT (address output signal) 704 is stored in the register 105a. After that, the data is sent to a bit operation executing part 107. Thereby, a user can handle the address of the data RAM in a decimal notation, and also, the control of a hardware can be simplified in comparison with a conventional computer system in which a decimal converter is connected through an I/O device.

44. 发明专利

JPH08278950A MULTIPLEXED COMPUTER SYSTEM AND FAULT RESTORING METHOD 失效
公开(公告)号：JPH08278950A
公开(公告)日：1996-10-22
申请号：JP7880395
申请日：1995-04-04
申请人： HITACHI LTD
发明人： MORITA YUICHIRO , YAMAGUCHI SHINICHIRO , NAKAMIGAWA TETSUAKI , MIYAZAKI NAOTO , TAKATANI SOICHI
IPC分类号： G06F15/16 , G06F11/18 , G06F15/177
摘要： PURPOSE: To eliminate the need for system resetting for synchronization and to perform a speedy resynchronization by transmitting an answer signal generated by accessing a specific address to plural arithmetic processors at the same time and resynchronizing arithmetic processors which have recovered from a fault. CONSTITUTION: For PIO access, the access acknowledgement wait state that an arithmetic processor is in until an access acknowledgement signal as a signal responding to an access request is received is utilized. The access acknowledgement signal for the PIO access is asserted to arithmetic processors 30a and 30b at the same time, and then the processors 30a and 30b are made to perform the PIO access at the same time, thereby synchronizing the processors 30a and 30b. Thus, the need for conventional resetting operation for synchronization is eliminated and both the processors can be synchronized by stopping ordinary operation in a short time.

45. 发明专利

JPH0816474A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH0816474A
公开(公告)日：1996-01-19
申请号：JP14735494
申请日：1994-06-29
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , KUROSAWA KENICHI , NAKAMIGAWA TETSUAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F15/16 , G06F12/08 , G06F15/163 , G06F15/177
摘要： PURPOSE:To guarantee matching at a high speed by storing data information which is registered in other clusters among data in the local memory of own cluster and deciding a range wherein cache memory contents should be matched. CONSTITUTION:A cluster 100 is constituted by connecting plural processors 200 equipped with cache memories 250, a cluster communication controller 500 equipped with an export directory 600, and a local memory 400 to a processor memory interface device 300. Then plural clusters 100 are connected to a cluster bus 2200 through the cluster communication controller 500 to form large-scale multiprocessor constitution on the whole. When data in the local memory in own cluster 100 are registered in the cache memory 250 of another cluster, the address of the data is registered in the export directory 600 and on the basis of the storage contents, the range wherein the contents of the cache memory 250 are matched is decided.

46. 发明专利

JPH03250221A BRANCH PREDICTING SYSTEM 失效
公开(公告)号：JPH03250221A
公开(公告)日：1991-11-08
申请号：JP4542490
申请日：1990-02-28
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , TANAKA SHIGEYA , KUROSAWA KENICHI , HOTTA TAKASHI , NAKATSUKA YASUHIRO , TAKEMOTO TAKESHI
IPC分类号： G06F9/38
摘要： PURPOSE:To improve the performance of calculation by defining the updating condition of a branch predicting table when the condition of a condition branching instruction is established and the branching destination is on the back of the instruction itself. CONSTITUTION:When the contents of an address branching instruction address (BIA) 1001 as a second instruction are coincident at time t2, an instruction address selector (IASEL) 105 sends the contents of a branching destination address (BTA) 1002 to an instruction address register (IAR) 106 as the address to be next read and in order to calculate the address to be next read, the contents are sent to an incrementer (INC) 104 as well. Further, for recovery in the case of failing prediction, the contents [(a)+4] of a program counter (PC) 103 are saved in a saving register (PCS) 108. In such a manner, reading is started from an predicted branching destination address (b) at time t3 and reading occurs from an address (b+4) at time t4. When the condition is established as the executed result of the second instruction at the time t4 and it is confirmed that branching occurs, the prediction is made successful. Thus, the condition branching is executed without useless waiting time and the performance of a computer is improved.

47. 发明专利

JPS62237528A DATA PROCESSING WITH TAG 失效
公开(公告)号：JPS62237528A
公开(公告)日：1987-10-17
申请号：JP7995286
申请日：1986-04-09
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , YAMAGUCHI SHINICHIRO , MATSUMOTO HIDEKAZU , BANDO TADAAKI
IPC分类号： G06F9/44
摘要： PURPOSE:To change a tag length on the basis of a program by providing the title data processor with a register for storing the tag length and a means for reading out the contents of the register. CONSTITUTION:A number '4' is set up as the tag length in a field TL123 indicating the length of the tag. The tag is extracted by a circuit EXTRACT 103 for extracting a tag part to extract 4 bits. The tag part is masked by a circuit MASK 102 for masking the tag. The high-order 4 bits of data are '0000' and the input 114 of the MASK 102 has the same contents as the output 115 of the MASK 102. In order to synthesize tags, the high-order 8 bits of a signal line 115 are ORed with contents obtained from a signal line 118. On the other hand, 'data + tag' is sent to a signal line 119. Since the previously determined length of the tap part can be optionally changed by the program, the optimum tag length for plural language processing systems can be selected without changing the design, and the dot in one word can be efficiently used.

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