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41. 发明授权

US08525170B2 Thin film transistor and manufacturing method thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08525170B2
公开(公告)日：2013-09-03
申请号：US12423829
申请日：2009-04-15
申请人： Shunpei Yamazaki , Yuji Egi , Shinya Sasagawa , Motomu Kurata
发明人： Shunpei Yamazaki , Yuji Egi , Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L29/04
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/41733 , H01L29/78696
摘要： Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.
摘要翻译：薄膜晶体管的截止电流减小，薄膜晶体管的导通电流增大，电特性的变化也降低。作为形成薄膜晶体管的沟道形成区域的半导体层的结构，在栅极绝缘层侧设置包括多个结晶区域的第一半导体层，在源区和漏区侧设置具有非晶结构的第二半导体层; 在第一半导体层和第二半导体层之间设置具有足够小以允许载流子行进的厚度的绝缘层。第一半导体层与栅极绝缘层接触。第二半导体层设置在与栅极绝缘层接触的与第一半导体层的面相反的一侧。

42. 发明授权

US08383491B2 Method for manufacturing semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US08383491B2
公开(公告)日：2013-02-26
申请号：US12564961
申请日：2009-09-23
申请人： Motomu Kurata , Shinya Sasagawa , Taiga Muraoka
发明人： Motomu Kurata , Shinya Sasagawa , Taiga Muraoka
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76254
摘要： A step of forming an insulating film over a semiconductor substrate and forming an embrittled region in the semiconductor substrate by irradiating the semiconductor substrate with accelerated ions through the insulating film; a step of disposing a surface of the semiconductor substrate and a surface of a base substrate opposite to each other and bonding the surface of the insulating film to the surface of the base substrate; a step of forming a semiconductor layer over the base substrate with the insulating film interposed therebetween by causing separation along the embrittled region by performing heat treatment after the surface of the insulating film and the surface of the base substrate are bonded to each other; a step of performing etching treatment on the semiconductor layer; a step of irradiating the semiconductor layer subjected to the etching treatment with a laser beam; and a step of irradiating the semiconductor layer irradiated with the laser beam with plasma.
摘要翻译：在半导体衬底上形成绝缘膜并在半导体衬底中形成脆化区域的步骤，通过将半导体衬底通过绝缘膜照射加速离子; 将所述半导体基板的表面和基板的表面相对配置并将所述绝缘膜的表面接合到所述基板的表面的工序; 通过在绝缘膜的表面和基底基板的表面彼此接合之后通过进行热处理沿着脆化区域分离而在绝缘膜上形成半导体层，其中绝缘膜介于其间; 在半导体层上进行蚀刻处理的步骤; 用激光束照射进行了蚀刻处理的半导体层的工序; 以及用等离子体照射用激光束照射的半导体层的步骤。

43. 发明申请

US20090325364A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20090325364A1
公开(公告)日：2009-12-31
申请号：US12490431
申请日：2009-06-24
申请人： Shinya Sasagawa , Motomu Kurata
发明人： Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： To provide a technical means which is capable of increasing crystallinity and planarity of a single crystal semiconductor layer, crystal defects are reduced in such a manner that a single crystal semiconductor substrate, in which an insulating film is formed on its surface and an embrittlement region is formed in a region at a predetermined depth from the surface, and a supporting substrate are attached to each other with the insulating film interposed therebetween; the single crystal semiconductor substrate is separated in the embrittlement region by a heat treatment; a single crystal semiconductor layer is irradiated with laser light over the supporting substrate with the insulating film interposed therebetween; a surface of the single crystal semiconductor layer is etched; and a plasma treatment is performed on the surface of the single crystal semiconductor layer.
摘要翻译：为了提供能够提高单晶半导体层的结晶性和平坦性的技术手段，晶体缺陷以这样的方式被降低，即在其表面上形成绝缘膜和脆化区域的单晶半导体衬底是形成在距离表面预定深度的区域中，并且支撑衬底彼此连接，绝缘膜插入其间; 通过热处理在脆化区域中分离单晶半导体衬底; 将单晶半导体层用激光照射在支撑基板上，绝缘膜插入其间; 蚀刻单晶半导体层的表面; 在单晶半导体层的表面进行等离子体处理。

44. 发明授权

US08829522B2 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US08829522B2
公开(公告)日：2014-09-09
申请号：US12972994
申请日：2010-12-20
申请人： Hidekazu Miyairi , Shinya Sasagawa , Motomu Kurata
发明人： Hidekazu Miyairi , Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L29/786
CPC分类号： H01L29/78678 , H01L29/66765 , H01L29/78618 , H01L29/78648
摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.
摘要翻译：提供了具有良好的电特性的高效生产的薄膜晶体管。薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层，以及与杂质半导体层接触的布线。半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。在半导体层和布线之间设置有阻挡区域。

45. 发明授权

US08653520B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08653520B2
公开(公告)日：2014-02-18
申请号：US13021343
申请日：2011-02-04
申请人： Shunpei Yamazaki , Teruyuki Fujii , Ryota Imahayashi , Shinya Sasagawa , Motomu Kurata , Fumika Taguchi
发明人： Shunpei Yamazaki , Teruyuki Fujii , Ryota Imahayashi , Shinya Sasagawa , Motomu Kurata , Fumika Taguchi
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0688 , G11C16/0416 , G11C16/0433 , G11C16/28 , H01L27/1052 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
摘要翻译：目的是提供一种具有新颖结构的半导体器件，其中包括氧化物半导体的晶体管和包括氧化物半导体之外的半导体材料的晶体管被堆叠。该半导体器件包括第一晶体管，第一晶体管上的绝缘层和绝缘层上的第二晶体管。在半导体器件中，第一晶体管包括第一沟道形成区，第二晶体管包括第二沟道形成区，第一沟道形成区包括与第二沟道形成区的半导体材料不同的半导体材料，绝缘层包括均方根表面粗糙度小于或等于1nm的表面。

46. 发明授权

US09437454B2 Wiring board, semiconductor device, and manufacturing methods thereof 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：US09437454B2
公开(公告)日：2016-09-06
申请号：US13161871
申请日：2011-06-16
申请人： Motomu Kurata , Shinya Sasagawa , Fumika Taguchi , Yoshinori Ieda
发明人： Motomu Kurata , Shinya Sasagawa , Fumika Taguchi , Yoshinori Ieda
IPC分类号： H01L29/10 , H01L21/3213 , H01L27/12
CPC分类号： H01L27/1288 , H01L21/31053 , H01L21/32135 , H01L21/32139 , H01L21/486 , H01L21/76885 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L27/1214 , H01L27/1225 , H01L27/124
摘要： It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.
摘要翻译：本发明的目的是减少集成度增加的布线板或半导体器件的导通不良。另一个目的是以高产率制造高度可靠的布线板或半导体器件。在具有多层布线结构的布线板或半导体器件中，具有弯曲表面的导电层用于连接用于布线的导电层。通过去除其周围的绝缘层而暴露的下层中的导电层的顶部具有弯曲表面，使得下层中的导电层与其上层叠的上层中的导电层的覆盖率可能是有利的。使用具有弯曲表面的抗蚀剂掩模蚀刻导电层，从而形成具有弯曲表面的导电层。

47. 发明授权

US09431545B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431545B2
公开(公告)日：2016-08-30
申请号：US13604962
申请日：2012-09-06
申请人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
发明人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
IPC分类号： H01L29/786 , H01L21/28 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225
摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.
摘要翻译：提供具有高电特性的小型化晶体管，其产率高。在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与氧化物半导体膜和侧壁绝缘层。在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

48. 发明授权

US08476744B2 Thin film transistor with channel including microcrystalline and amorphous semiconductor regions 有权
标题翻译：具有通道的薄膜晶体管包括微晶和非晶半导体区域
公开(公告)号：US08476744B2
公开(公告)日：2013-07-02
申请号：US12978049
申请日：2010-12-23
申请人： Hiekazu Miyairi , Shinya Sasagawa , Motomu Kurata , Asami Tadokoro
发明人： Hiekazu Miyairi , Shinya Sasagawa , Motomu Kurata , Asami Tadokoro
IPC分类号： H01L21/02
CPC分类号： H01L29/78609 , H01L29/66765 , H01L29/78618 , H01L29/78669 , H01L29/78678
摘要： A thin film transistor with favorable electric characteristics is provided. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer which includes a microcrystalline semiconductor region and an amorphous semiconductor region, an impurity semiconductor layer, a wiring, a first oxide region provided between the microcrystalline semiconductor region and the wiring, and a second oxide region provided between the amorphous semiconductor region and the wiring, wherein a line tangent to the highest inclination of an oxygen profile in the first oxide region (m1) and a line tangent to the highest inclination of an oxygen profile in the second oxide region (m2) satisfy a relation of 1
摘要翻译：提供具有良好电特性的薄膜晶体管。薄膜晶体管包括栅电极，栅极绝缘层，包括微晶半导体区域和非晶半导体区域的半导体层，杂质半导体层，布线，设置在微晶半导体区域和布线之间的第一氧化物区域以及设置在所述非晶半导体区域和所述布线之间的第二氧化物区域，其中与所述第一氧化物区域（m1）中的氧分布的最高倾斜度相切的直线和与所述第一氧化物区域第二氧化物区域（m2）在半导体层侧满足包括在布线中的元素的轮廓与包含在半导体层中的元素的轮廓的交点的1

49. 发明授权

US08343849B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08343849B2
公开(公告)日：2013-01-01
申请号：US12490431
申请日：2009-06-24
申请人： Shinya Sasagawa , Motomu Kurata
发明人： Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： To provide a technical means which is capable of increasing crystallinity and planarity of a single crystal semiconductor layer, crystal defects are reduced in such a manner that a single crystal semiconductor substrate, in which an insulating film is formed on its surface and an embrittlement region is formed in a region at a predetermined depth from the surface, and a supporting substrate are attached to each other with the insulating film interposed therebetween; the single crystal semiconductor substrate is separated in the embrittlement region by a heat treatment; a single crystal semiconductor layer is irradiated with laser light over the supporting substrate with the insulating film interposed therebetween; a surface of the single crystal semiconductor layer is etched; and a plasma treatment is performed on the surface of the single crystal semiconductor layer.
摘要翻译：为了提供能够提高单晶半导体层的结晶性和平坦性的技术手段，晶体缺陷以这样的方式被降低，即在其表面上形成绝缘膜和脆化区域的单晶半导体衬底是形成在距离表面预定深度的区域中，并且支撑衬底彼此连接，绝缘膜插入其间; 通过热处理在脆化区域中分离单晶半导体衬底; 将单晶半导体层用激光照射在支撑基板上，绝缘膜插入其间; 蚀刻单晶半导体层的表面; 在单晶半导体层的表面进行等离子体处理。

50. 发明授权

US08247308B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08247308B2
公开(公告)日：2012-08-21
申请号：US12505020
申请日：2009-07-17
申请人： Akihiro Ishizuka , Shinya Sasagawa , Motomu Kurata , Atsushi Hikosaka , Taiga Muraoka , Hitoshi Nakayama
发明人： Akihiro Ishizuka , Shinya Sasagawa , Motomu Kurata , Atsushi Hikosaka , Taiga Muraoka , Hitoshi Nakayama
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.
摘要翻译：本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿着脆化区域分离，由此在基底基板上形成半导体层氧化膜。

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