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41. 发明授权

US09368379B2 Systems and methods of controlling semiconductor wafer fabrication processes 有权
标题翻译：控制半导体晶圆制造工艺的系统和方法
公开(公告)号：US09368379B2
公开(公告)日：2016-06-14
申请号：US13419952
申请日：2012-03-14
申请人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
发明人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
IPC分类号： G06F15/00 , G01B11/26 , H01L21/67 , H01L21/68 , H01L21/687
CPC分类号： H01L21/67259 , H01L21/681 , H01L21/68764
摘要： A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.
摘要翻译：一种控制半导体晶片制造工艺的系统和方法。该方法包括将半导体晶片定位在晶片处理模块中的晶片支撑组件上。信号从相对于垂直于晶片支撑组件的轴线以预定的传输角定位的信号发射器传输，以检查模块中晶片的调平，使得信号从晶片反射。该实施例包括在信号接收器处相对于垂直于晶片支撑组件的轴以预定的反射角监视反射信号。如果在信号接收器处未接收到反射信号，则会产生警告指示。

42. 发明授权

US09111597B2 Memory device structure with decoders in a device level separate from the array level 有权
标题翻译：存储器件结构，其中解码器的器件级别与阵列级别分开
公开(公告)号：US09111597B2
公开(公告)日：2015-08-18
申请号：US13721523
申请日：2012-12-20
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , G11C8/10 , G11C5/02
CPC分类号： G11C8/10 , G11C5/025
摘要： A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.
摘要翻译：描述了一种用于制造存储器件结构的存储器件结构和方法。存储器件结构具有设置在阵列级的存储器阵列和设置在器件级的外围电路，包括解码器和其它外围电路。存储器单元阵列具有限定在存储器单元阵列上方和下方延伸的圆柱体的周边。解码器和其它外围电路或解码器和其它外围电路的至少一部分设置在装置级内的气缸内。存储器件结构还包括垫级别中的多个焊盘。第一多个级间导电线将解码器电耦合到存储器单元阵列中的位线和字线。

43. 发明授权

US08987787B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08987787B2
公开(公告)日：2015-03-24
申请号：US13443496
申请日：2012-04-10
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
IPC分类号： H01L27/118 , H01L23/52 , H01L23/34 , H01L23/48 , H01L29/40 , H01L21/00 , H01L21/336 , H01L21/3205 , H01L23/522 , H01L23/00 , H01L25/065 , H01L25/18 , H01L27/105 , H01L27/02
CPC分类号： H01L23/522 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L27/0203 , H01L27/1052 , H01L2224/0401 , H01L2224/04042 , H01L2224/06177 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/73207 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1435 , H01L2924/1443
摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
摘要翻译：半导体结构包括彼此组装的第一和第二芯片。第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。第二和第一导电线形成重叠区域。第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

44. 发明申请

US20130277852A1 Method for Creating a 3D Stacked Multichip Module 有权
标题翻译：创建3D堆叠多芯片模块的方法
公开(公告)号：US20130277852A1
公开(公告)日：2013-10-24
申请号：US13451411
申请日：2012-04-19
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/16146 , H01L2224/24011 , H01L2224/24146 , H01L2224/2919 , H01L2224/32145 , H01L2224/33181 , H01L2224/82031 , H01L2224/821 , H01L2224/83005 , H01L2224/83191 , H01L2224/8385 , H01L2224/9202 , H01L2225/06544 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014 , H01L2224/82
摘要： A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
摘要翻译： 3D堆叠多芯片模块包括一堆W IC芯片。每个管芯具有图案化导体层，其包括与电导体的电接触区域，并且在一些示例中包括衬底上的器件电路。堆叠管芯的电导体对齐。电连接器延伸到堆叠中以接触电导体上的着陆焊盘，以产生3D堆叠多芯片模块。电连接器可以穿过电接触区域中的垂直通孔。着陆垫可以布置成阶梯式的台阶。堆叠的多芯片模块可以使用一组N个蚀刻掩模制成，其中2N-1小于W且2N大于或等于W，其中蚀刻掩模交替地覆盖并暴露每个掩模的2n-1个着陆焊盘n = 1，2。。。 N.

45. 发明授权

US08168538B2 Buried silicide structure and method for making 有权
标题翻译：埋地硅化物结构及其制造方法
公开(公告)号：US08168538B2
公开(公告)日：2012-05-01
申请号：US12472158
申请日：2009-05-26
申请人： Shih-Hung Chen , Tian-Jue Hong
发明人： Shih-Hung Chen , Tian-Jue Hong
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L27/101 , H01L21/743 , H01L21/8221 , H01L27/0688 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675 , H01L45/1683
摘要： Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.
摘要翻译：本文描述了用于制造掩埋硅化物线的方法，以及高密度堆叠存储器结构。如本文所述的用于制造集成电路的方法包括形成包括硅的半导体本体。在半导体本体中形成多个沟槽以限定在相邻沟槽之间包括硅的半导体线，半导体线具有侧壁。在沟槽内沉积硅化物前体以接触半导体管线的侧壁，并且去除硅化物前体的一部分以暴露侧壁的上部，并沿侧壁留下剩余的硅化物前体条。然后通过引起硅化物条与半导体线的硅的反应形成硅化物导体。

46. 发明申请

US20120080716A1 INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION 审中-公开
标题翻译：用于片上ESD保护的初始化SCR器件
公开(公告)号：US20120080716A1
公开(公告)日：2012-04-05
申请号：US13327171
申请日：2011-12-15
申请人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
发明人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
IPC分类号： H01L29/772
CPC分类号： H01L23/62 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
摘要翻译：一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接到PMOS晶体管的第二扩散区域。

47. 发明授权

US08097871B2 Low operational current phase change memory structures 有权
标题翻译：低工作电流相变存储器结构
公开(公告)号：US08097871B2
公开(公告)日：2012-01-17
申请号：US12433573
申请日：2009-04-30
申请人： Shih-Hung Chen , Yi-Chou Chen
发明人： Shih-Hung Chen , Yi-Chou Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/122 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1616 , H01L45/1641 , H01L45/1675 , Y10S977/943
摘要： Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.
摘要翻译：与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。因此，引起相变所需的电流量减少。

48. 发明授权

US07804083B2 Phase change memory cell including a thermal protect bottom electrode and manufacturing methods 有权
标题翻译：相变存储单元包括热保护底电极和制造方法
公开(公告)号：US07804083B2
公开(公告)日：2010-09-28
申请号：US11940164
申请日：2007-11-14
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L47/00 , H01L29/04 , H01L31/036
CPC分类号： H01L45/143 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the thermal protect material having a thermal conductivity less than that of the bottom electrode material.
摘要翻译：存储器件与制造方法一起被描述。如本文所述的存储器件的实施例包括底部电极，底部电极上的热保护结构以及热保护结构上的多层堆叠。热保护结构包括一层热保护材料，该热保护材料的热导率小于底部电极材料的热导率。

49. 发明授权

US07786460B2 Phase change memory device and manufacturing method 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07786460B2
公开(公告)日：2010-08-31
申请号：US11621390
申请日：2007-01-09
申请人： Hsiang Lan Lung , Shih-Hung Chen
发明人： Hsiang Lan Lung , Shih-Hung Chen
IPC分类号： H01L21/06 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1691
摘要： A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.
摘要翻译：相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于彼此之间并将电极的相对接触元件彼此电耦合的相变元件。相变元件具有宽度，长度和厚度。长度，厚度和宽度小于用于形成相变存储器单元的工艺的最小光刻特征尺寸。可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变元件的长度和宽度都小于最小光刻特征尺寸。

50. 发明申请

US20100117048A1 MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
标题翻译：具有多晶和单晶半导体区域的PN结的存储器单元访问器件
公开(公告)号：US20100117048A1
公开(公告)日：2010-05-13
申请号：US12267453
申请日：2008-11-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
IPC分类号： H01L45/00 , H01L29/04 , H01L21/329
CPC分类号： H01L29/8616 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L29/04 , H01L29/165 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.
摘要翻译：存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

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