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41. 发明专利

JPS61104500A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS61104500A
公开(公告)日：1986-05-22
申请号：JP22220084
申请日：1984-10-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C29/00 , G11C29/04
摘要： PURPOSE: To obtain a semiconductor integrated circuit which incorporates a memory circuit using a fuse means of high reliability, by short-circuiting the both ends of the fuse means to set the same potential at these ends after discriminating the presence/absence of the fusing of the fuse means and preventing an electric field of a high level produced at a minute cut gap.
CONSTITUTION: The presence or absence of fusing is decided for a fuse means F by turning on or off a MOSFETQ2 according to a defective address signal a0 while the power supply voltage Vcc is supplied to an electrode P2. If the means F has no fusing, for example, this state of the means F is held by a storage action owing to a low level of the output (node N3) of a gate circuit G1. While the high-level signal of the output of an exclusive OR circuit EX is delayed through a delay circuit DL. Thus a node N5, i.e., the output of the circuit DL has a rise up to a high level with a delay to turn on a MOSFETQ7 which short-circuits substantially both ends of the means F. As a result, the potentials at both ends of the means F are set at approximately equal level.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了获得一种使用具有高可靠性的保险丝装置的存储电路的半导体集成电路，通过使熔丝装置的两端短路，在将这些端部的存在/不存在熔断器意味着并且防止在微小间隙产生的高电平的电场。构成：通过在将电源电压Vcc提供给电极P2的同时，根据缺陷地址信号a0接通或关断MOSFETQ2来确定熔丝装置F的存在或不存在。如果装置F没有熔断，例如，由于门电路G1的输出（节点N3）的低电平，装置F的这种状态被存储动作保持。而异或电路EX的输出的高电平信号通过延迟电路DL延迟。因此，节点N5，即电路DL的输出已经上升到高电平，具有延迟以导通MOSFETQ7，这使得装置F的实质上两端短路。结果，两端的电位装置F被设定在大致相等的水平。

42. 发明专利

JPS59117794A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59117794A
公开(公告)日：1984-07-07
申请号：JP22630182
申请日：1982-12-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C29/781
摘要： PURPOSE:To decrease the number of electrode of a storage circuit using a fuse means by controlling the supply of a blown current to a fuse via common electrode incorporated in each address comparison storing a failed address. CONSTITUTION:When an address a0' inputted to an address compare ACO or the like is at a low level and a failed address, an FETQ2 is turned off and an FETQ3 is turned on. Then, a blown current is applied to a fuse F via a common electrode P2 and it is cut off and this failed state is stored by FETQ4, Q5 of cross connection forming an FF. A prescribed voltage from the common electrodes P3, P2 is impressed to an RAM finished for the write. The number of electrodes of the storage circuit including a redundancy section using a fuse means is saved by the constitution using the common electrode.
摘要翻译：目的：通过使用熔丝装置减少存储电路的电极数量，通过在每个地址比较中并入存储故障地址的公共电极控制向熔丝供应熔断电流。构成：当输入到地址比较ACO等的地址a0'处于低电平且失败的地址时，FETQ2被关断，FETQ3导通。然后，通过公共电极P2将熔断电流施加到熔断器F，并将其断开，并且该故障状态由形成FF的交叉连接的FETQ4，Q5存储。来自公共电极P3，P2的规定电压施加到完成写入的RAM。包括使用熔丝装置的冗余部分的存储电路的电极数量通过使用公共电极的结构来节省。

43. 发明专利

JPH09167490A DYNAMIC RAM 失效
公开(公告)号：JPH09167490A
公开(公告)日：1997-06-24
申请号：JP27822796
申请日：1996-10-21
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/409 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To provide a dynamic ram wherein the operation is stabilized by installing transfer gates MOSFETs which are connected to respective complementary data lines in a memory array which divides a sense amplifier and supplying a precharge level to the complementary lines in a non-selection condition. SOLUTION: In a chip non-selected condition, the transfer gates MOSFETs, Q5 to Q8, and, Q9 to Q12, which are connected to the complementary data lines of memory arrays, MARY-L, R, which divide the sense amplifier SA are made 'on'. When one memory array is in the non-selection condition, switches MOSFERTs Q14, 15 become 'off' because the operation timing signal ϕpa of the sense amplifier SA is at the low level and the timing signal ϕpa is at the high level. By this, the input/output node of the sense amplifier SA becomes high in impedance. After that, the precharge MOSFETs Q16, 17 become 'on' and can supply half-precharge level by the level compensating circuit to the complementary data lines on the non-selections side for continuous access, stabilizing operations.

44. 发明专利

JPH0816486A LSI FOR DEFECT REMEDY AND MEMORY DEVICE 失效
公开(公告)号：JPH0816486A
公开(公告)日：1996-01-19
申请号：JP17020794
申请日：1994-06-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , KEMIZAKI KANEHIDE , MURANAKA MASAYA , OGATA SHINKO , AOYANAGI HIDEAKI , KITAME TETSUYA , KATAYAMA MASAHIRO , KUBONO SHIYOUJI , SUZUKI YUKIE , MORINO MAKOTO , MIYATAKE SHINICHI , HARUFUJI SEIICHI , KOYAMA YOSHIHISA , ONO NOBUHIKO
IPC分类号： G06F12/16 , G11C29/00 , G11C29/02 , G11C29/44 , H01L21/82
摘要： PURPOSE:To provide an LSI which can remedy a defect of a mounted DRAM and to provide a memory device which can remedy the defect of the DRAM generated after assembly. CONSTITUTION:The LSI for defect remedy consists of an interface part for the same address and control with DRAMs, an input/output interface corresponding to the memory device consisting of plural DRAMs, a nonvolatile storage circuit 3 which stores the chip addresses of the DRAMs and a defect address of an X system, a RAM part 4 for redundancy remedy consisting of an SRAM which has a word line selected with a comparison matching signal between an inputted X address and the defect address of the storage circuit and a column selected with a Y address signal, a selection part 6 which connects the data input/output bus of the RAM part for redundancy to a data input/output terminal, a data input/output part 7 which activates an input/output circuit corresponding to the selection, and a mask part 8 which outputs a signal for placing the output terminal of a DRAM judged to be defective in a high-impedance state.

45. 发明专利

JPH0668667A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0668667A
公开(公告)日：1994-03-11
申请号：JP24275192
申请日：1992-08-19
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： TSUNOSAKI MANABU , ISHII KYOKO , NOZAKI KOICHI , YOSHIOKA HIROSHI , KOYAMA YOSHIHISA , UDO SHINJI , AOYANAGI HIDETOMO , MIYATAKE SHINICHI , MORINO MAKOTO , HOSHIDA AKIHIKO
IPC分类号： G11C11/401 , G11C5/02 , H01L27/108
摘要： PURPOSE:To provide large storage capacity while attaining stabilized and high speed operation with a small area. CONSTITUTION:A DRAM cell is composed of a memory matrix with matrix- shaped arrangement and plural sets of sense amplifiers, provided with a selecting means for transmitting or stopping to transmit a signal from the respective sense amplifiers 2 and a Y selection line 1 transferring a selecting signal and a decoding circuit for selection is arranged almost in the middle part of the Y selection line 1. Respective X, Y address buffers are adjacent to the position nearer to the mid section of a chip than respective X, Y redundant circuits. A generating circuit for a reference voltage is arranged nearer to the end part of the chip than an output buffer circuit and a selecting circuit for relieving each redundant line in each memory matrix is arranged adjacently in every objective memory matrix. A part of wiring in the amplifier 2 is composed of the same wiring layer as that of the Y selection line 1 and the Y selection line passes through the spacing of the sense amplifier group. A shared MOS 5 and a data line precharging MOS 6 have the same specification of the quantity of impurity ion implantation and ion species as that of the memory cell.

46. 发明专利

JPH0628849A DYNAMIC TYPE RAM 失效
公开(公告)号：JPH0628849A
公开(公告)日：1994-02-04
申请号：JP20722792
申请日：1992-07-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI , KOYAMA YOSHIHISA
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406
摘要： PURPOSE:To allow a dynamic type cell memory to hold information with a high reliability by providing a tire circuit at a part where heat radiating condition is bad on a semiconductor substrate. CONSTITUTION:A tire circuit 4 is provided at the central part of a semiconductor chip 1 on the worst condition of the radiation of heat. When a dynamic type RAM is switched from an operating state to a data holding mode (automatic refresh mode), the part remains to be a high temperature until the end of a temperature distribution generated by the chip 1. Then, a refresh cycle corresponding to the high temperature is decided by arranging the tire circuit 4 at the pertinent part. Therefore, it is not necessary to set the refresh cycle longer than the refresh time of the memory cell arranged at an area where the radiating condition is satisfactory.

47. 发明专利

JPH04155859A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04155859A
公开(公告)日：1992-05-28
申请号：JP28148690
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , MATSUURA NOBUMI , II HARUO , MURANAKA MASAYA , ABE JUNICHI , SUZUKI YUKIE , ARAI KOJI , YOSHIKAWA KAZUE
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance an electrostatic breakdown preventive circuit in breakdown strength by a method wherein the distance between the connection region of a second semiconductor region connected to an outer terminal and the peripheral edge nearest to the connection region is set equal to or larger than the junction depth of the second semiconductor region at the connection region. CONSTITUTION:A P-type well region 3 higher than a P -type semiconductor substrate 1 in impurity concentration is formed on a first region of the primary surface of the P -type semiconductor substrate 1, and an N-type well region 2 is formed on a second region of the primary surface of the P -type semiconductor substrate 1. The N-type well region 2 forms the protective resistive element R of an electrostatic breakdown protecting circuit 30, where the one end of the element R is connected to an external terminal BP provided to the primary surface and the other end is connected to an input stage circuit 31. A distance L2 between the connection region (N -type semiconductor region 8) of the N-type well region 2 which serves as the element R of the electrostatic breakdown protective circuit 30 and the nearest periphery is set equal to or larger than the junction depth L1 of the N-type well region 2 at the connection region.

48. 发明专利

JPH0258377A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0258377A
公开(公告)日：1990-02-27
申请号：JP20843288
申请日：1988-08-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA KATSUTAKA , IWAI HIDETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/522 , G11C11/401 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize high speed advancement of operation speed of a semiconductor integrated circuit device having DRAM by making wiring layers at the first and second layers into the wiring layers for signal transmission which are connected electrically at every specified interval. CONSTITUTION:In DRAM1, standard clock signal generating circuits (RAS and/or CAS) which are arranged respectively on opposite short sides of a rectangular chip and address circuits (XAB, YAB) are provided extendedly along the long side of the rectangular chip and are connected with standard clock signal wires in short-circuited two-layer wiring structure. Hereby, the resistance value of the standard clock signal wiring is reduced as compared with the case of single layer wiring structure, and high speed advancement of the transmission speed of standard clock signals is achieved. Hereby, the margin of address set-up time and address hold time improves, and high speed advancement of the operation speed of the DRAM1 can be achieved.

49. 发明专利

JPS6480041A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480041A
公开(公告)日：1989-03-24
申请号：JP23590187
申请日：1987-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA MASATAKA , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To prevent the disconnection of aluminum wiring at the second layer in a part which is stepped because of aluminum wiring at the first layer, by causing the thickness of aluminum wiring at the first layer to be thinner than that of aluminum wiring at the second layer. CONSTITUTION:Aluminum wiring Al 1 at the first layer is mounted on a layer insulation film 3 and aluminum wiring Al 2 at the second layer is mounted on the layer insulation film 4. In such a case, this device allows the thickness of wiring Al 1 to be thinner than that of wiring of Al 2. Then, a stepped part which is caused by wiring Al 1 at the base surface of wiring Al 2 becomes small. Thus, this situation serves the purpose of improving the step coverage of wiring Al 2 at the stepped part and accordingly, preventing the disconnection of wiring Al 2 at the stepped part.

50. 发明专利

JPS6325883A DYNAMIC RAM 失效
公开(公告)号：JPS6325883A
公开(公告)日：1988-02-03
申请号：JP16798486
申请日：1986-07-18
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MIYATAKE SHINICHI , KOYAMA YOSHIHISA
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To enlarge an action margin by precharging a dummy capacity to the power source voltage of a circuit with an MOSFET made into an ON condition when a sense amplifier is an action condition. CONSTITUTION:To a common source line PS at a P channel MOSFET side, a dummy capacity Cp is selectively connected through a switch MOSFET Q46. The capacity value of the dummy capacity Cp is set so that the synthetic capacity value of it and the parasitic capacity of a common source line PS at a P channel MOSFET side is made approximately equal to the parasitic capacity value at an N channel MOSFET side. The precharging action to the dummy capacity Cp is executed by a P channel type switch MOSFET Q47 to receive a timing signal phip. The timing signal phip is set from a high level to a low level after a sense amplifier SA starts an action. Thus, the peak current at the time of starting the action of the sense amplifier cam be minimized.

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