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41. 发明申请

US20080049521A1 METHOD FOR COMPACTING THE ERASED THRESHOLD VOLTAGE DISTRIBUTION OF FLASH MEMORY DEVICES DURING WRITING OPERATIONS 有权
标题翻译：写入操作期间闪存存储器件的擦除阈值电压分配方法
公开(公告)号：US20080049521A1
公开(公告)日：2008-02-28
申请号：US11844480
申请日：2007-08-24
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
IPC分类号： G11C16/04
CPC分类号： G11C16/344
摘要： A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.
摘要翻译：一种用于操作闪存设备的方法。存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元目标值将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

42. 发明申请

US20070035995A1 METHOD OF PROGRAMMING A FOUR-LEVEL FLASH MEMORY DEVICE AND A RELATED PAGE BUFFER 审中-公开
标题翻译：编程四级闪存存储器件和相关页面缓冲器的方法
公开(公告)号：US20070035995A1
公开(公告)日：2007-02-15
申请号：US11460835
申请日：2006-07-28
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10 , G11C11/5628
摘要： A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage VS on the source node is negligible, and the programmed state of the cell may be correctly verified.
摘要翻译：四级FLASH存储器件包括可单独寻址的预擦除存储器单元的阵列，每个存储器单元能够存储两位数据。当验证存储器单元的阈值电压达到期望分布时，使用小于或等于编程电压的测试读取电压来读取单元。在这种情况下，源节点上的电压V SUB可忽略不计，并且可以正确验证单元的编程状态。

43. 发明申请

US20070030732A1 Double page programming system and method 有权
标题翻译：双页编程系统和方法
公开(公告)号：US20070030732A1
公开(公告)日：2007-02-08
申请号：US11495876
申请日：2006-07-28
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.
摘要翻译：一种用于编程电可编程存储器的方法，包括布置在各自包括至少一个存储单元的可单独选择的存储单元组中的多个存储单元。编程方法包括使所设置的选定存储单元的存储单元进入预定的开始编程状态。接收所选存储器单元的存储单元的第一数据位组的目标值。接收所选存储器单元的存储单元的第二数据位组的目标值。在接收到第一和第二数据位组两者的目标值之后，将所选择的存储器单元的存储单元应用到所设置的编程顺序，以使所选择的存储单元组的存储器单元进入目标编程状态由第一和第二数据位组的目标值联合确定。

44. 发明授权

US06642776B1 Bandgap voltage reference circuit 有权
标题翻译：带隙电压参考电路
公开(公告)号：US06642776B1
公开(公告)日：2003-11-04
申请号：US09541577
申请日：2000-04-03
申请人： Rino Micheloni , Luca Crippa
发明人： Rino Micheloni , Luca Crippa
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.
摘要翻译：带隙电压参考电路，输出电压在使用温度范围内保持稳定。电路包括第一电路块，第二电路块和与所述电路块连接的控制电路，所述第一电路块包括具有低功耗的带隙电路，所述第二电路块包括具有短启动的带隙电路所述控制电路适于以这样的方式控制所述两个电路块，使得所述带隙电压参考电路的所述输出电压在所述第一电路块的启动期间由所述第二电路块提供一段时间，并且所述输出电压由所述第一电路块供给所述时间段之后的时间段，并持续到所述电路的断开，所述第二电路块在所述时间段之后被关断。

45. 发明授权

US08621318B1 Nonvolatile memory controller with error detection for concatenated error correction codes 有权
标题翻译：具有错误检测功能的非易失性存储器控制器，用于级联纠错码
公开(公告)号：US08621318B1
公开(公告)日：2013-12-31
申请号：US13435572
申请日：2012-03-30
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.
摘要翻译：一种非易失性存储器控制器，用于通过执行硬判决内纠错码解码和使用硬判决内纠错码解码解码的数据的外纠错码解码来恢复编码数据，然后确定编码数据是否已成功解码。如果编码数据尚未成功解码，则控制器使用软判决算法和使用软判决内部误差解码的数据的外部纠错码解码来对编码数据执行软判决内部纠错码解码校正码解码，然后确定编码数据是否已被成功解码。如果编码数据尚未成功解码，则控制器通过对编码数据执行RAID操作来恢复数据。

46. 发明授权

US07730357B2 Integrated memory system 有权
标题翻译：集成内存系统
公开(公告)号：US07730357B2
公开(公告)日：2010-06-01
申请号：US10805182
申请日：2004-03-19
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G06F11/1048
摘要： An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.
摘要翻译：本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

47. 发明授权

US07444543B2 Data control unit capable of correcting boot errors, and corresponding self-correction method 有权
标题翻译：能够修正启动错误的数据控制单元及相应的自校正方法
公开(公告)号：US07444543B2
公开(公告)日：2008-10-28
申请号：US11149948
申请日：2005-06-09
申请人： Irene Babudri , Marco Roveda , Rino Micheloni
发明人： Irene Babudri , Marco Roveda , Rino Micheloni
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , G06F11/076
摘要： A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory into a volatile memory through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit verifies whether the boot information downloaded into its volatile memory has a critical-error condition and activates a spare memory portion of the nonvolatile memory in presence of the critical-error condition.
摘要翻译：用于数据控制单元的引导方法将引导信息从非易失性存储器下载到引导启动单元的临时缓冲器中。处理单元由启动激活单元激活; 由处理单元执行引导代码; 并且通过引导启动单元将操作代码从非易失性存储器下载到易失性存储器中。为了纠正包含信息和引导代码的非易失性存储器的块中的可能错误，引导激活单元验证下载到其易失性存储器中的引导信息是否具有关键错误状况，并在存在时激活非易失性存储器的备用存储器部分的关键错误条件。

48. 发明授权

US07068540B2 Method and device for programming an electrically programmable non-volatile semiconductor memory 有权
标题翻译：用于编程电可编程非易失性半导体存储器的方法和装置
公开(公告)号：US07068540B2
公开(公告)日：2006-06-27
申请号：US10729829
申请日：2003-12-05
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1–MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.
摘要翻译：用于编程电可编程存储器的装置和方法将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC 1 -MC k），访问该组的存储器单元以确定其编程状态，并应用于至少一秒编程脉冲到组中编程状态未被确定以对应于期望的编程状态的那些存储器单元。根据在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，施加到所述存储器单元的控制电极的电压在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间变化和至少一个第二编程脉冲。因此避免了对存储器单元的不期望的过度编程。

49. 发明授权

US07027317B2 Semiconductor memory with embedded DRAM 失效
标题翻译：具有嵌入式DRAM的半导体存储器
公开(公告)号：US07027317B2
公开(公告)日：2006-04-11
申请号：US10720013
申请日：2003-11-20
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C11/24 , G11C14/00
CPC分类号： G11C11/005
摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.
摘要翻译：半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

50. 发明授权

US07017099B2 Method for error control in multilevel cells with configurable number of stored bits 有权
公开(公告)号：US07017099B2
公开(公告)日：2006-03-21
申请号：US10159782
申请日：2002-05-30
申请人： Rino Micheloni , Massimiliano Picca , Roberto Ravasio , Stefano Zanardi
发明人： Rino Micheloni , Massimiliano Picca , Roberto Ravasio , Stefano Zanardi
IPC分类号： H03M13/00
CPC分类号： G06F11/1072 , G11C2211/5641
摘要： A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

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