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41. 发明授权

US08599909B2 Serial link voltage margin determination in mission mode 有权
标题翻译：任务模式下的串行链路电压裕度确定
公开(公告)号：US08599909B2
公开(公告)日：2013-12-03
申请号：US12850535
申请日：2010-08-04
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H04B3/46
CPC分类号： H04L25/03057 , H04L25/061 , H04L25/14
摘要： This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.
摘要翻译：本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

42. 发明授权

US08595534B2 Method for system energy use management of current shared power supplies 有权
标题翻译：目前共享电源系统能源使用管理方法
公开(公告)号：US08595534B2
公开(公告)日：2013-11-26
申请号：US12886843
申请日：2010-09-21
申请人： Drew G. Doblar , Michael Bushue
发明人： Drew G. Doblar , Michael Bushue
IPC分类号： G06F1/26
CPC分类号： G06F11/3062 , G06F1/3206 , G06F11/3051 , G06F11/3082
摘要： A non-transitory computer readable storage medium having computer readable program code embodied therein, where the computer readable program code is adapted to, when executed by a processor, implement a method for managing a power supply system. The method includes identifying a number of power supplies included in the power supply system, and determining a first system mode for the power supply system. The method also includes determining a first operating order for the power supplies, and assigning a first ACTIVE ON threshold to each of the power supplies to obtain a number of first ACTIVE ON thresholds. The method further includes assigning a first ACTIVE STANDBY OFF threshold to each of the power supplies to obtain a number of first ACTIVE STANDBY OFF thresholds, where the power supply system provides electrical power to at least one computer system.
摘要翻译：一种具有体现在其中的计算机可读程序代码的非瞬时计算机可读存储介质，其中计算机可读程序代码在由处理器执行时实施用于管理电源系统的方法。该方法包括识别包括在电源系统中的多个电源，以及确定供电系统的第一系统模式。该方法还包括确定电源的第一操作顺序，以及为每个电源分配第一ACTIVE ON阈值以获得多个第一ACTIVE ON阈值。该方法还包括为每个电源分配第一ACTIVE STANDBY OFF阈值以获得多个第一ACTIVE STANDBY OFF阈值，其中电源系统向至少一个计算机系统提供电力。

43. 发明授权

US08446985B2 Method and system for reducing duty cycle distortion amplification in forwarded clocks 有权
标题翻译：用于减少转发时钟中占空比失真放大的方法和系统
公开(公告)号：US08446985B2
公开(公告)日：2013-05-21
申请号：US12343426
申请日：2008-12-23
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0008 , G06F1/10 , H04L25/061
摘要： A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
摘要翻译：提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。数据信号通过第一通道发送到接收器。时钟信号通过第二通道发送到接收器。在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

44. 发明授权

US08243866B2 Analog baud rate clock and data recovery 有权
标题翻译：模拟波特率时钟和数据恢复
公开(公告)号：US08243866B2
公开(公告)日：2012-08-14
申请号：US12116329
申请日：2008-05-07
申请人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
发明人： Dawei Huang , Zuxu Qin , Drew G. Doblar , Waseem Ahmad , Dong Joon Yoon , Osman Javed
IPC分类号： H04L7/00 , H04L27/06
CPC分类号： H04L7/0062
摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.
摘要翻译：模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。从第一和第二电位定时误差信号导出期望的定时误差信号。所需的定时误差信号用于确定信号采样是早还是晚。

45. 发明授权

US08234096B2 Extraction of component models from PCB channel scattering parameter data by stochastic optimization 有权
标题翻译：通过随机优化从PCB通道散射参数数据中提取组件模型
公开(公告)号：US08234096B2
公开(公告)日：2012-07-31
申请号：US12608364
申请日：2009-10-29
申请人： Juyoung Lee , Drew G. Doblar
发明人： Juyoung Lee , Drew G. Doblar
IPC分类号： H04B15/00 , G01R27/00 , G01R27/28 , G01R27/04
CPC分类号： G06F17/5077 , G01R23/163 , G06F2217/10 , G06F2217/82
摘要： Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data.
摘要翻译：本文的各种实施例包括从从物理PCB通道获取的测量（或模拟）中提取用于PCB通道的组件（例如，通孔和迹线）的模型的系统，方法，软件和/或数据结构中的一个或多个。通过对具有不同信道长度的两个PCB信道的测量应用随机优化，可以通过搜索多维度来准确地确定PCB信道的组件的s矩阵（例如，两端口，四端口等）符合测量值的参数的参数空间。一旦已经准确地确定了组件的模型，它们可以用于构建包括组件模型并且基于物理测量数据的模型库。

46. 发明授权

US08229020B2 Integrated equalization and CDR adaptation engine with single error monitor circuit 有权
标题翻译：具有单错误监控电路的集成均衡和CDR适配引擎
公开(公告)号：US08229020B2
公开(公告)日：2012-07-24
申请号：US12409236
申请日：2009-03-23
申请人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
发明人： Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
IPC分类号： H04B15/00 , H04B1/10 , H03K5/159
CPC分类号： H04L25/03057 , H04L7/0337 , H04L2025/03503
摘要： A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.
摘要翻译：公开了一种数据通信系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

47. 发明授权

US08218702B2 System and method of adapting precursor tap coefficient 有权
标题翻译：适应前驱抽头系数的系统和方法
公开(公告)号：US08218702B2
公开(公告)日：2012-07-10
申请号：US12388223
申请日：2009-02-18
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04L7/00
CPC分类号： H04L7/0062
摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.
摘要翻译：公开了一种从输入数据信号中恢复数据的系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。该相位基于从数据信号恢复的时钟。响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

48. 发明授权

US08155214B2 Asymmetric decision feedback equalization slicing in high speed transceivers 有权
标题翻译：高速收发器中的非对称判决反馈均衡切片
公开(公告)号：US08155214B2
公开(公告)日：2012-04-10
申请号：US12612449
申请日：2009-11-04
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/03878 , H04L25/03146
摘要： An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.
摘要翻译：公开了一种不对称DFE接收器电路。接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。调整速率可以根据接收到的信号是转换位还是非转换位而变化。

49. 发明申请

US20120068544A1 AUTONOMOUS CONTROL IN CURRENT SHARE POWER SUPPLIES 有权
标题翻译：当前共享电源的自动控制
公开(公告)号：US20120068544A1
公开(公告)日：2012-03-22
申请号：US12886730
申请日：2010-09-21
申请人： Michael Bushue , Drew G. Doblar
发明人： Michael Bushue , Drew G. Doblar
IPC分类号： H02J4/00
CPC分类号： H02J1/102 , H02J3/46 , H02J9/005 , H02M1/4225 , Y02B70/126 , Y10T307/50 , Y10T307/696
摘要： A method for autonomous control by a power supply unit (PSU) among a number of current share PSUs in a power supply system. The method includes: Receiving input power from a power input feed; setting a mode of the PSU to ON; receiving a first controlled signal including a first number of IStar modes and thresholds; receiving a first activation signal activating IStar in the PSU; receiving a second controlled signal comprising a first voltage; determining that the first voltage is less than a first Active standby OFF threshold for an IStar mode of Active standby OFF; setting the IStar mode for the PSU to Active standby OFF; receiving a third controlled signal that includes a second voltage; determining that the second voltage is greater than a first Active ON threshold for an IStar mode of Active ON; and setting the IStar mode for the PSU to Active ON.
摘要翻译：一种供电系统中多个当前共享PSU中的电源单元（PSU）的自主控制的方法。该方法包括：从电源输入馈电接收输入电源; 将PSU的模式设置为ON; 接收包括第一数量的IStar模式和阈值的第一受控信号; 接收在PSU中激活IStar的第一激活信号; 接收包括第一电压的第二受控信号; 确定第一电压小于用于主动待机OFF的IStar模式的第一活动待机OFF阈值; 将PSU的IStar模式设置为主动待机OFF; 接收包括第二电压的第三受控信号; 确定所述第二电压大于用于激活ON的IStar模式的第一有效开启阈值; 并将PSU的IStar模式设置为“有效”。

50. 发明授权

US07822110B1 Eye diagram determination during system operation 有权
标题翻译：系统运行期间的眼图确定
公开(公告)号：US07822110B1
公开(公告)日：2010-10-26
申请号：US11243036
申请日：2005-10-04
申请人： Drew G. Doblar
发明人： Drew G. Doblar
IPC分类号： H04B3/46
CPC分类号： H04B3/32 , H04B3/466
摘要： A system for testing a communications link. A system includes a transmitter, a receiver, a digital communications link, and a service processor. The digital communications link includes a plurality of lanes through which the transmitter is coupled to the receiver. During an operating mode of the digital communications link and during otherwise normal system operation, the service processor (a) switches a selected one of the plurality of lanes from the operating mode to a test mode, (b) performs an eye scan of the selected lane, (c) stores data corresponding to the eye scan of the selected lane, and (d) returns the selected lane to the operating mode.
摘要翻译：用于测试通信链路的系统。系统包括发射机，接收机，数字通信链路和服务处理器。数字通信链路包括多个通道，发射器通过该通道耦合到接收器。在数字通信链路的操作模式期间和在其它正常系统操作期间，服务处理器（a）将多个通道中的所选择的一个从操作模式切换到测试模式，（b）对所选择的通道，（c）存储对应于所选车道的眼睛扫描的数据，以及（d）将所选车道返回到操作模式。

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