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41. 发明授权

US06985009B2 Signal transmitting system 失效
标题翻译：信号传输系统
公开(公告)号：US06985009B2
公开(公告)日：2006-01-10
申请号：US10816187
申请日：2004-04-02
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H03K17/16
CPC分类号： H04L5/16 , G11C7/1006 , H04L25/0278
摘要： Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line. The semiconductor integrated circuit devices use a common reference voltage for determining the signal voltage.
摘要翻译：在不同电源电压下工作的半导体集成电路器件通过作为传输线的双向总线直接互连。驱动器是推挽式的，接收端是CTT端接的。如果终端电阻符合传输线的特性阻抗，则驱动器的导通电阻等于或低于特性阻抗。如果驱动器的导通电阻与传输线的特性阻抗一致，则终端电阻的值等于或低于传输线的特性阻抗。如果接收侧是VTT终止的，则VTT的值是提供给各个半导体集成电路器件的电源电压中的较低一个的1/2。终端电阻的值与传输线的特性阻抗一致。半导体集成电路器件使用公共参考电压来确定信号电压。

42. 发明授权

US06970369B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06970369B2
公开(公告)日：2005-11-29
申请号：US10234261
申请日：2002-09-04
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/06 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175 , D11C5/06
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/10 , G11C11/4093
摘要： In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.
摘要翻译：在具有控制器和多个存储器模块的存储器件中，两者都被安装在母板上，通过抑制由信号反射引起的波形失真来执行高速操作。由于当控制器执行相对于存储器模块上的存储器单元的数据的写入/读取时发生信号反射，因此主动终端单元包括在控制器和存储器单元中。这些有源终端单元被提供用于数据总线和/或时钟总线，以便在存储器单元中终止这些总线。当要接收数据时，为控制器和存储单元提供的有效终端单元可能会处于非活动状态。

43. 发明授权

US06707726B2 Register without restriction of number of mounted memory devices and memory module having the same 有权
标题翻译：在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册
公开(公告)号：US06707726B2
公开(公告)日：2004-03-16
申请号：US10206823
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
摘要翻译：第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。因此，命令/地址信号被分解成一组暂时具有两次的信号。例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号，时间和保持时间充分确保。

44. 发明授权

US06519173B2 Memory system 有权
公开(公告)号：US06519173B2
公开(公告)日：2003-02-11
申请号：US10161634
申请日：2002-06-05
申请人： Seiji Funaba , Yoji Nishio , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yoshinobu Nakagome
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , H01L2224/16225 , H01L2924/13091 , H05K1/0216 , H05K1/14 , H01L2924/00
摘要： A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

45. 发明授权

US06359815B1 Data transmitter 有权
标题翻译：数据发送器
公开(公告)号：US06359815B1
公开(公告)日：2002-03-19
申请号：US09646010
申请日：2000-09-12
申请人： Takashi Sato , Yoji Nishio , Yoshinobu Nakagome
发明人： Takashi Sato , Yoji Nishio , Yoshinobu Nakagome
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22
摘要： When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high speeds in a short period, in particular, the setup time for receiving the data and the holding time are no longer maintained, and the data are not normally transmitted. In a data transmitter provided to address this problem, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit for comparing phases of part or whole bits of the received data, and with a timing adjusting mechanism for adjusting phases among the parallel bits at a point of receiving data in the receiver based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at the receiver. Even when there is a difference in the lengths of the paths or in the load capacities, therefore, the setup time for receiving data and the holding time are maintained.
摘要翻译：当并行数据配线中的通道长度差异或包含寄生元件的负载电容的差异时，数据之间的传播时间差不再可忽略。在短时间内以高速发送数据的时候，特别是不再保持接收数据的建立时间和保持时间，并且数据不被正常发送。在用于解决该问题的数据发送机中，用于接收并行数据的接收机具有用于比较接收数据的部分或全部比特的相位的同时到达判断电路，以及用于调整并行位之间的相位的定时调整机构在接收机中基于同时到达判断电路的判断结果接收数据的点，使得数据位同时到达接收机。因此，即使路径的长度或负载能力存在差异，也能够保持接收数据的建立时间和保持时间。

46. 发明授权

US06046609A Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06046609A
公开(公告)日：2000-04-04
申请号：US188369
申请日：1998-11-10
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

47. 发明授权

US5963483A Synchronous memory unit 失效
标题翻译：同步存储单元
公开(公告)号：US5963483A
公开(公告)日：1999-10-05
申请号：US133952
申请日：1998-08-14
申请人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
发明人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.
摘要翻译：一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器来自选择器的数据信号根据时钟信号。输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。输出缓冲器从输出锁存器接收并输出放大的输出数据信号。每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

48. 发明授权

US08953406B2 Semiconductor module includes semiconductor chip initialized by reset signal 有权
标题翻译：半导体模块包括由复位信号初始化的半导体芯片
公开(公告)号：US08953406B2
公开(公告)日：2015-02-10
申请号：US13455985
申请日：2012-04-25
申请人： Yoji Nishio , Takao Hirayama , Susumu Hatano , Haruki Nagahashi , Masashi Kawamura , Tadaaki Yoshimura
发明人： Yoji Nishio , Takao Hirayama , Susumu Hatano , Haruki Nagahashi , Masashi Kawamura , Tadaaki Yoshimura
IPC分类号： G11C8/00 , G06F13/40
CPC分类号： G06F13/4086
摘要： Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.
摘要翻译：这里公开了一种装置，其包括安装在模块基板上的多个半导体芯片。每个半导体芯片包括提供复位信号的复位端子和基于复位信号而被初始化的内部电路。模块基板包括与半导体芯片的复位端子共同连接的复位信号线以及连接到复位信号线的反谐振元件。

49. 发明授权

US08878351B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08878351B2
公开(公告)日：2014-11-04
申请号：US12318700
申请日：2009-01-06
申请人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
发明人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
IPC分类号： H01L23/02 , H01L23/50 , H01L23/498 , H01L25/065 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01055 , H01L2924/15311 , H01L2224/05599
摘要： A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.
摘要翻译：具有片上芯片结构的半导体器件由第一半导体芯片和偶数对的第二半导体芯片组成，所有第二半导体芯片在中介层的表面上层压在一起。第一半导体芯片控制每对第二半导体芯片，以激活一个第二半导体芯片，同时使另一个第二半导体芯片失效。第二半导体芯片以通孔和电极通过凸块彼此相对定位的方式配对在一起。由于提供有驱动电压（VDD）的驱动电压电极和提供参考电位（VSS）的参考电位电极在成对的第二半导体芯片之间相互连接在一起，因此可以增加每个第二半导体芯片的总静电电容以便在不增加半导体器件的整体布局面积的情况下显着降低馈送噪声。

50. 发明授权

US08738347B2 Method for extracting IBIS simulation model 有权
标题翻译：提取IBIS仿真模型的方法
公开(公告)号：US08738347B2
公开(公告)日：2014-05-27
申请号：US13354109
申请日：2012-01-19
申请人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
发明人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
IPC分类号： G06F17/50 , G06F3/06 , G06F5/06 , G06F5/16 , G06F7/78 , G06F9/54 , G06F13/16
CPC分类号： G06F3/0656 , G06F5/06 , G06F5/065 , G06F5/16 , G06F7/78 , G06F9/544 , G06F13/1673 , G06F17/50 , G06F17/5036 , G06F2003/0691 , G06F2205/062 , G06F2205/063 , G06F2205/066
摘要： A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
摘要翻译：一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。

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