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41. 发明授权

US5513377A Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus 失效
标题翻译：输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位
公开(公告)号：US5513377A
公开(公告)日：1996-04-30
申请号：US261561
申请日：1994-06-17
申请人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
发明人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
IPC分类号： H04L29/00 , G06F13/42 , H04L7/00 , G06F13/00
CPC分类号： G06F13/423
摘要： An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.
摘要翻译：增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的模块化宽带输入/输出元件，可以经济地服务于两个通道，并可模块化地扩展以提供数百个通道。

42. 发明授权

US07478259B2 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

43. 发明授权

US06922789B2 Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface 有权
标题翻译：用于重新校准源同步流水线自定时总线接口的装置和方法
公开(公告)号：US06922789B2
公开(公告)日：2005-07-26
申请号：US09960023
申请日：2001-09-21
申请人： Patrick J. Meaney , Jonathan Chen , Frank D. Ferraiolo , Kevin C. Gower , Glenn E. Holmes
发明人： Patrick J. Meaney , Jonathan Chen , Frank D. Ferraiolo , Kevin C. Gower , Glenn E. Holmes
IPC分类号： G06F11/00 , H04L7/10 , H04L7/00 , G06F13/00
CPC分类号： H04L7/10 , G06F11/00 , H04L7/0008
摘要： An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.
摘要翻译： SMP计算机系统具有在计算机系统运行时重新校准自定时，源同步，流水线接口的装置和方法。该设备允许停顿接口（即空闲处理器以允许不进行数据传输），提高栅栏（阻塞接口），允许快速的时钟定心重新校准步骤，然后解码和解码以允许使用接口再次。重新校准可以补偿接口上随时间的漂移，以补偿温度，电压，循环时间和使用寿命结束后的降低，而不会导致系统重新启动和重新启动。

44. 发明授权

US06807125B2 Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效
标题翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法
公开(公告)号：US06807125B2
公开(公告)日：2004-10-19
申请号：US10225871
申请日：2002-08-22
申请人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
发明人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
摘要翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法。该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号期。电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。

45. 发明授权

US06285229B1 Digital delay line with low insertion delay 失效
标题翻译：具有低插入延迟的数字延迟线
公开(公告)号：US06285229B1
公开(公告)日：2001-09-04
申请号：US09471898
申请日：1999-12-23
申请人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
发明人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00058
摘要： A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.
摘要翻译：一种可变数字延迟线，其插入延迟低至单个延迟元件，但能够利用小的简单控制机制提供大的可编程延迟。环路通过可选择的第一延迟元件（例如2：1多路复用器）和可选择的第二延迟元件（例如成对的反相器）通过具有抽头的多个中间节点将输入连接到输出。多个潜行路径是可用的，其中循环通过中间节点处的抽头通过第一延迟元件的剩余部分和/或第二延迟元件。

46. 发明授权

US5870404A Self-timed circuit having critical path timing detection 失效
标题翻译：具有关键路径定时检测的自定时电路
公开(公告)号：US5870404A
公开(公告)日：1999-02-09
申请号：US694120
申请日：1996-08-08
申请人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
发明人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
IPC分类号： G06F1/08 , G06K5/04 , G11B5/00
CPC分类号： G06F1/08
摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.
摘要翻译：公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

47. 发明授权

US5694087A Anti-latching mechanism for phase lock loops 失效
标题翻译：锁相环锁止机构
公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
IPC分类号： H03L7/10 , H03L7/093
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译：用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。在失控状态下，计数器不复位，并触发VCO的控制信号。第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。当第一个计数器远远超出第二个计数器时，触发控制信号。

48. 发明授权

US5577078A Edge detector 失效
标题翻译：边缘检测器
公开(公告)号：US5577078A
公开(公告)日：1996-11-19
申请号：US452446
申请日：1995-05-26
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.
摘要翻译：边缘检测器具有数字锁相环，其中信号之一（例如，数据信号）耦合到产生输入的一系列增量相位延迟版本的延迟链。选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中的数据信号的边沿之间，或在所选相位对的边缘之外，在其一侧或另一侧上。如果时钟沿落在所选择的对之外，则控制信号选择另一对进行比较，并且重复处理，直到例如数据沿与时钟的正向边对齐。在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。

49. 发明授权

US5487095A Edge detector 失效
公开(公告)号：US5487095A
公开(公告)日：1996-01-23
申请号：US262087
申请日：1994-06-17
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

50. 发明授权

US5272729A Clock signal latency elimination network 失效
标题翻译：时钟信号延迟消除网络
公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译：描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部时钟信号输入到半导体芯片一个周期。描述和要求保护各种定时网络实施例。

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