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41. 发明申请

US20080157354A1 Multiple stacked nanostructure arrays and methods for making the same 审中-公开
标题翻译：多层叠纳米结构阵列及其制造方法
公开(公告)号：US20080157354A1
公开(公告)日：2008-07-03
申请号：US11649523
申请日：2007-01-03
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L27/00 , H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , G01N27/127 , H01L29/0673 , H01L29/0676 , H01L31/03529 , Y02E10/50
摘要： A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.
摘要翻译：一种叠层纳米结构阵列的制造方法包括：制备衬底; 直接在基板上形成底部电极; 直接在底部电极上生长第一个纳米结构阵列; 在所述第一纳米结构阵列上形成绝缘层; 暴露第一纳米结构阵列的上表面; 在第二和随后的纳米结构阵列正下方的纳米结构阵列上沉积第二和随后的纳米结构阵列; 重复所述形成，所述曝光和沉积随后的步骤以形成堆叠的纳米结构阵列; 去除最上层绝缘层; 并在最上面的纳米结构阵列上形成顶部电极。结合纳米结构阵列的传感器包括其间具有多层纳米结构阵列的顶部和底部电极。

42. 发明授权

US07379320B2 Method for operating an MFIS ferroelectric memory array 有权
标题翻译：用于操作MFIS铁电存储器阵列的方法
公开(公告)号：US07379320B2
公开(公告)日：2008-05-27
申请号：US11262117
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

43. 发明授权

US07364924B2 Silicon phosphor electroluminescence device with nanotip electrode 有权
标题翻译：具有纳米尖电极的硅荧光体电致发光器件
公开(公告)号：US07364924B2
公开(公告)日：2008-04-29
申请号：US11061946
申请日：2005-02-17
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H01L21/00
CPC分类号： H05B33/145
摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
摘要翻译：提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。在一个方面，Si磷光体层是SRSO层。响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

44. 发明授权

US07208372B2 Non-volatile memory resistor cell with nanotip electrode 失效
标题翻译：带纳米尖电极的非易失性存储器电阻单元
公开(公告)号：US07208372B2
公开(公告)日：2007-04-24
申请号：US11039544
申请日：2005-01-19
申请人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
发明人： Sheng Teng Hsu , Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff
IPC分类号： H01L21/06 , H01L21/461
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
摘要翻译：提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

45. 发明授权

US06906366B2 Single transistor ferroelectric transistor structure with high-k insulator 失效
标题翻译：具有高k绝缘体的单晶体管铁电晶体管结构
公开(公告)号：US06906366B2
公开(公告)日：2005-06-14
申请号：US10441661
申请日：2003-05-20
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/3105 , H01L21/316 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/02189 , H01L21/02197 , H01L21/02271 , H01L21/0228 , H01L21/28291 , H01L21/31053 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/66545 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

46. 发明授权

US06819583B2 Ferroelectric resistor non-volatile memory array 失效
标题翻译：铁电电阻非易失性存储器阵列
公开(公告)号：US06819583B2
公开(公告)日：2004-11-16
申请号：US10345726
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
摘要翻译：铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

47. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

48. 发明授权

US06759250B2 Deposition method for lead germanate ferroelectric structure with multi-layered electrode 失效
标题翻译：具有多层电极的锗酸铅铁电结构沉积方法
公开(公告)号：US06759250B2
公开(公告)日：2004-07-06
申请号：US10196503
申请日：2002-07-15
申请人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31604 , H01L21/31691 , H01L28/75
摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
摘要翻译：提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。还提供了形成上述多层电极铁电体结构体的方法。

49. 发明授权

US06720258B2 Method of fabricating a nickel silicide on a substrate 有权
标题翻译：在衬底上制造硅化镍的方法
公开(公告)号：US06720258B2
公开(公告)日：2004-04-13
申请号：US10319313
申请日：2002-12-12
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.
摘要翻译：集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有任何取向偏好，从而形成均匀的硅化镍层。可以将镍硅化物退火以形成均匀的结晶二硅化镍。因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

50. 发明授权

US06682995B2 Iridium conductive electrode/barrier structure and method for same 失效
标题翻译：铱导电电极/屏障结构及方法相同
公开(公告)号：US06682995B2
公开(公告)日：2004-01-27
申请号：US10317742
申请日：2002-12-11
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.
摘要翻译：已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。还提供了形成多层Ir导电结构和Ir铁电电极的方法。

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