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41. 发明授权

US5831295A Current confinement via defect generator and hetero-interface interaction 失效
标题翻译：通过缺陷发生器和异质界面相互作用的电流限制
公开(公告)号：US5831295A
公开(公告)日：1998-11-03
申请号：US566388
申请日：1995-12-01
申请人： Jenn-Hwa Huang , Saied N. Tehrani
发明人： Jenn-Hwa Huang , Saied N. Tehrani
IPC分类号： H01L23/62 , H01L31/0328 , H01L23/48 , H01L31/0336
CPC分类号： H01L23/62 , H01L2924/0002
摘要： A semiconductor device including a plurality of layers of material defining a diffusion barrier. A defect generator positioned on the plurality of layers in overlying relationship to the diffusion barrier so as to produce a collection of defects at the diffusion barrier that operates as a current restriction. In a typical example, an ohmic contact is positioned around the mesa of a ridge VCSEL, which ohmic contact generates defects that accumulate at a hetero-interface near the active area and confine the current flow to a lasing volume of the VCSEL.
摘要翻译：一种包括限定扩散阻挡层的多层材料的半导体器件。一种缺陷发生器，其以与扩散阻挡层重叠的关系位于多个层上，以便在作为电流限制的扩散阻挡层产生缺陷的集合。在典型的示例中，欧姆接触定位在脊VCSEL的台面周围，该欧姆接触产生在有源区附近的异质界面处积累的缺陷，并将电流限制到VCSEL的激光体积。

42. 发明授权

US5768181A Magnetic device having multi-layer with insulating and conductive layers 失效
标题翻译：具有多层绝缘导电层的磁性器件
公开(公告)号：US5768181A
公开(公告)日：1998-06-16
申请号：US834968
申请日：1997-04-07
申请人： Theodore Zhu , Saied N. Tehrani
发明人： Theodore Zhu , Saied N. Tehrani
IPC分类号： G11C11/15 , G11C11/56 , G11C7/00
CPC分类号： G11C11/15 , G11C11/5607 , G11C2211/5615
摘要： A magnetic device (40) having multi-layer (41-45) with insulating layer (45) and conductive layer (42). The conductive layer (42) is positioned between a first magnetic layer (41) and a third magnetic layer (44). The insulating layer (45) is positioned between a second magnetic layer (43) and the third magnetic layer (44), and which forms a tunnel junction between the second and third layers. Magnetic vectors in the first magnetic layer (41) magnetically couple with ones in the second magnetic layer (43) so that the magnetic coupling loop formed around the third magnetic layer (44) allows magnetic vectors in the third magnetic layer (44) to be switchable in a low magnetic field. Consequently, total power consumption of the magnetic device (60) decreases.
摘要翻译：具有绝缘层（45）和导电层（42）的具有多层（41-45）的磁性装置（40）。导电层（42）位于第一磁性层（41）和第三磁性层（44）之间。绝缘层（45）位于第二磁性层（43）和第三磁性层（44）之间，并且在第二层和第三层之间形成隧道结。第一磁性层（41）中的磁矢量与第二磁性层（43）中的磁性磁耦合，使得围绕第三磁性层（44）形成的磁耦合环允许第三磁性层（44）中的磁矢量为可在低磁场中切换。因此，磁性装置（60）的总功耗降低。

43. 发明授权

US5748519A Method of selecting a memory cell in a magnetic random access memory device 失效
标题翻译：选择磁性随机存取存储器件中的存储单元的方法
公开(公告)号：US5748519A
公开(公告)日：1998-05-05
申请号：US766637
申请日：1996-12-13
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L21/78
CPC分类号： G11C11/15
摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.
摘要翻译：提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。

44. 发明授权

US5659179A Ultra-small semiconductor devices having patterned edge planar surfaces 失效
标题翻译：具有图案化边缘平坦表面的超小型半导体器件
公开(公告)号：US5659179A
公开(公告)日：1997-08-19
申请号：US399809
申请日：1995-03-07
申请人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
发明人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
IPC分类号： H01L29/06 , H01L21/329 , H01L27/06 , H01L29/88
CPC分类号： H01L29/66219 , H01L27/0605 , H01L29/882
摘要： Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型半导体器件和制造方法包括图案化衬底的平坦表面以形成图案边缘（例如台面）并且以与图案边缘重叠的关系连续地形成多个半导体材料层，使得不连续性为在图案边缘的一侧上产生的层和第一层与图案边缘的另一侧上的不同层对准并与之接触。

45. 发明授权

US5326985A Bipolar doped semiconductor structure and method for making 失效
标题翻译：双极掺杂半导体结构及其制造方法
公开(公告)号：US5326985A
公开(公告)日：1994-07-05
申请号：US951994
申请日：1992-09-28
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
IPC分类号： H01L29/778 , H01L29/161 , H01L29/205
CPC分类号： H01L29/7783
摘要： A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.D) and to provide holes to the first undoped channel (11,14) when the second material composition has a valence band maximum greater than the doping energy level (E.sub.D).
摘要翻译：提供了从单个掺杂剂源提供N型和P型掺杂的半导体结构。包括第一材料组合物的第一掺杂区域（13）包括掺杂能级（ED）的空穴和电子 - 包含第一材料组合物的第一未掺杂间隔区域（12）覆盖掺杂区域（13）。包括第二材料组合物的未掺杂通道（11,14）覆盖第一间隔区域（12），并且包括第一材料组合物的第二未掺杂间隔区域（12）覆盖未掺杂沟道（11,14）。第一材料组合物具有比第二材料组成更宽的带隙，并且当第二材料组合物具有小于掺杂能量的导带最小值时，选择掺杂能级（ED）以向未掺杂沟道（11,14）提供电子（ED），并且当第二材料组合物具有大于掺杂能级（ED）的价带最大值时，向第一未掺杂通道（11,14）提供孔。

46. 发明授权

US5081511A Heterojunction field effect transistor with monolayers in channel region 失效
标题翻译：通道区域中具有单层的异质结场效应晶体管
公开(公告)号：US5081511A
公开(公告)日：1992-01-14
申请号：US578167
申请日：1990-09-06
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/12 , H01L29/36 , H01L29/43 , H01L29/778
CPC分类号： B82Y10/00 , H01L29/122 , H01L29/432 , H01L29/66462 , H01L29/7783 , H01L29/365
摘要： A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel comprises a quantum well and at least one mono-atomic well or barrier layer is provided. The mono-atomic well or barrier layer has a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, an indium arsenide well monolayer is formed in an InGaAs channel region and functions to move a first quantized energy level E.sub.0 closer to the bottom of the channel region quantum well thereby increasing electron concentration by increasing effective band offset potential. Another embodiment uses an aluminum arsenide monolayer as a barrier monolayer in the InGaAs channel. By varying location of the monolayers, confinement of electrons in the channel can be improved.

47. 发明授权

US5978257A Multi-layer magnet tunneling junction memory cells 失效
标题翻译：多层磁铁隧道结存储单元
公开(公告)号：US5978257A
公开(公告)日：1999-11-02
申请号：US28426
申请日：1998-02-24
申请人： Xiaodong T. Zhu , Herbert Goronkin , Saied N. Tehrani
发明人： Xiaodong T. Zhu , Herbert Goronkin , Saied N. Tehrani
IPC分类号： G11C11/15 , G11C11/16 , G11C11/56 , H01L21/8246
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16 , G11C11/5607 , H01L27/224 , G11C2211/5615 , G11C2211/5616
摘要： A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.
摘要翻译：一种多态多层磁存储单元，包括第一导体，与第一导体接触的第一磁性层，第一磁性层上的绝缘层，绝缘层上的第二磁性层，与第二磁性体接触的第二导体层，以及与单元相邻或接触的字线，以便提供磁场以沿着第一磁性层的长度部分地切换磁矢量。通过使一条电流通过字线并通过第一和第二导体的第二电流足以切换第一和第二磁性层中的矢量来存储信息。通过使读取电流通过足以通过第一和第二导体切换一层（而不是另一层）和感测电流通过电池的读取电流，并测量电池两端的电阻来实现感测。

48. 发明授权

US5897366A Method of resistless gate metal etch for fets 失效
标题翻译：用于花边的无阻栅极金属蚀刻方法
公开(公告)号：US5897366A
公开(公告)日：1999-04-27
申请号：US813400
申请日：1997-03-10
申请人： Kumar Shiralagi , Saied N. Tehrani
发明人： Kumar Shiralagi , Saied N. Tehrani
IPC分类号： H01L21/308 , H01L21/335 , H01L21/20
CPC分类号： H01L29/66462 , H01L21/3086
摘要： A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.
摘要翻译：公开了在场效应晶体管的形成中的抗电镀栅极金属蚀刻的方法，其包括提供具有表面的第一半导体材料的第一层。在表面上形成第二层第二半导体材料，并且无阻地构图以限定掩模和未掩模部分。第二层的未掩模部分被蚀刻掉到第一层以实现栅极形成。

49. 发明授权

US5640025A High frequency semiconductor transistor 失效
标题翻译：高频半导体晶体管
公开(公告)号：US5640025A
公开(公告)日：1997-06-17
申请号：US566386
申请日：1995-12-01
申请人： Majid M. Hashemi , Saied N. Tehrani
发明人： Majid M. Hashemi , Saied N. Tehrani
IPC分类号： H01L29/737 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7371
摘要： A high frequency transistor including a heavily doped first current carrying layer positioned on a substrate and a semi-insulating layer of LTGaAs epitaxially grown on the first layer. The semi-insulating layer is etched, using a layer of AlAs as an etch stop, to define an active region and a first current carrying electrode is grown on the exposed first layer in the active region. A control layer is grown on the semi-insulating layer and the first current carrying electrode, and a second current carrying electrode is grown on the control layer. External contacts are formed on the first current carrying layer, the control layer, and the second current carrying electrode.
摘要翻译：包括位于衬底上的重掺杂的第一载流层和在第一层上外延生长的LTGaAs的半绝缘层的高频晶体管。使用AlAs层作为蚀刻停止层来蚀刻半绝缘层以限定有源区，并且在有源区中暴露的第一层上生长第一载流电极。控制层生长在半绝缘层上，第一载流电极和第二载流电极在控制层上生长。外部触点形成在第一载流层，控制层和第二载流电极上。

50. 发明授权

US5482875A Method for forming a linear heterojunction field effect transistor 失效
标题翻译：用于形成线性异质结场效应晶体管的方法
公开(公告)号：US5482875A
公开(公告)日：1996-01-09
申请号：US229266
申请日：1994-04-18
申请人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
发明人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08 , H01L29/10 , H01L29/778 , H01L29/80 , H01L21/335
CPC分类号： H01L29/7783 , H01L29/0891 , H01L29/1029 , Y10S148/072
摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
摘要翻译：低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于栅极源极电压大约在所需工作点处的相对最大值。

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