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41. 发明申请

US20060292800A1 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US20060292800A1
公开(公告)日：2006-12-28
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

42. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

43. 发明申请

US20140042629A1 SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US20140042629A1
公开(公告)日：2014-02-13
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

44. 发明授权

US07754545B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07754545B2
公开(公告)日：2010-07-13
申请号：US11949090
申请日：2007-12-03
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L21/339 , H01L21/84
CPC分类号： H01L27/11573 , H01L21/3144
摘要： A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.
摘要翻译：提供半导体器件及其制造方法。首先，在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。接下来，氮化物层被氧化。氮化物层中的氮化物的一部分移动到第一氧化物层和基底。氮化物层的上部被转换为上部氧化物层。然后，除去第二区域中的上氧化物层，氮化物层和第一氧化物层。其次，在第二区域的基底上生长第二氧化物层。第二区域中的氮化物移动到第二氧化物层。

45. 发明授权

US07556999B2 Method for fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07556999B2
公开(公告)日：2009-07-07
申请号：US11531007
申请日：2006-09-12
申请人： Yen-Hao Shih , Erh-Kun Lai
发明人： Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L21/823462 , H01L27/105 , H01L27/11573
摘要： A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the memory region. Thereafter, a buried diffusion region is formed in the substrate of the memory area. A charge trapping layer and a third insulating layer are formed over the substrate. A gate insulating layer is formed in the second region in the peripheral area, wherein the first thickness is greater than a second thickness after removing the charge trapping layer and third insulating layer on the first and second region in the peripheral area. A conductive layer is formed over the substrate of the memory area and the peripheral area substantially after the gate insulating layer is formed.
摘要翻译：一种用于制造具有存储区域和周边区域的存储器的方法包括在周边区域中的第一区域的衬底上形成具有第一厚度的第一栅极绝缘层和在衬底上形成具有第二厚度的第二绝缘层记忆区域。此后，在存储区域的基板中形成掩埋扩散区域。电荷俘获层和第三绝缘层形成在衬底上。在周边区域的第二区域中形成栅极绝缘层，其中在除去周边区域中的第一和第二区域上的电荷俘获层和第三绝缘层之后，第一厚度大于第二厚度。在形成栅极绝缘层之后，在存储区域的基板和外围区域上形成导电层。

46. 发明授权

US07521321B2 Method of fabricating a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US07521321B2
公开(公告)日：2009-04-21
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

47. 发明申请

US20090075466A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090075466A1
公开(公告)日：2009-03-19
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

48. 发明申请

US20080157184A1 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
标题翻译：操作具有氧化物/氮化物多层绝缘结构的非易失性存储单元的方法
公开(公告)号：US20080157184A1
公开(公告)日：2008-07-03
申请号：US11649348
申请日：2007-01-03
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chin Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chin Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/0475 , G11C16/14 , H01L21/28282 , H01L29/4234 , H01L29/513
摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.
摘要翻译：公开了一种通过向栅极施加足以使栅极向电荷存储层进行空穴隧道的正电压来操作存储单元的方法。该方法应用于包括半导体层的存储单元，该半导体层具有设置在半导体层的表面下方并由沟道区分隔开的至少两个源极/漏极区域。存储单元还具有设置在沟道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 设置在电荷存储层上方的上绝缘多层结构。上绝缘多层结构包括下介电层和设置在下介电层上的上氮化物层，并且存储单元具有设置在上绝缘多层结构上方的栅极。

49. 发明申请

US20080064158A1 METHOD FOR FABRICATING NON-VOLATILE MEMORY 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20080064158A1
公开(公告)日：2008-03-13
申请号：US11531007
申请日：2006-09-12
申请人： Yen-Hao Shih , Erh-Kun Lai
发明人： Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8242
CPC分类号： H01L27/11568 , H01L21/823462 , H01L27/105 , H01L27/11573
摘要： A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the memory region. Thereafter, a buried diffusion region is formed in the substrate of the memory area. A charge trapping layer and a third insulating layer are formed over the substrate. A gate insulating layer is formed in the second region in the peripheral area, wherein the first thickness is greater than a second thickness after removing the charge trapping layer and third insulating layer on the first and second region in the peripheral area. A conductive layer is formed over the substrate of the memory area and the peripheral area substantially after the gate insulating layer is formed.
摘要翻译：一种用于制造具有存储区域和周边区域的存储器的方法包括在周边区域中的第一区域的衬底上形成具有第一厚度的第一栅极绝缘层和在衬底上形成具有第二厚度的第二绝缘层记忆区域。此后，在存储区域的基板中形成掩埋扩散区域。电荷俘获层和第三绝缘层形成在衬底上。在周边区域的第二区域中形成栅极绝缘层，其中在除去周边区域中的第一和第二区域上的电荷俘获层和第三绝缘层之后，第一厚度大于第二厚度。在形成栅极绝缘层之后，在存储区域的基板和外围区域上形成导电层。

50. 发明授权

US07279385B2 Flash memory device and manufacturing method thereof 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US07279385B2
公开(公告)日：2007-10-09
申请号：US11018536
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11521 , H01L29/42376
摘要： A method of manufacturing a flash memory device is provided. Multiple stack structures each comprising a tunneling oxide layer and a first conductive layer are formed over a substrate. Thereafter, multiple embedded doping regions is formed in the substrate between the stack structures. A dielectric layer is formed over the substrate to cover the stack structures and then the dielectric layer is etched back and a portion of dielectric layer is remained on the stack structures. Using a portion of the remaining dielectric layer as a mask, a portion of the first conductive layer is removed. An inter-layer dielectric layer and a second conductive layer are sequentially formed over the first conductive layer. Because a self-aligned process is used to define the floating gate and the floating gate has a narrow-top/wide-bottom configuration, the fabrication process is simplified and the coupling ratio of the stack gate is increased.
摘要翻译：提供一种制造闪速存储器件的方法。在衬底上形成各自包括隧穿氧化物层和第一导电层的堆叠结构。此后，在堆叠结构之间的衬底中形成多个嵌入的掺杂区域。在衬底上形成电介质层以覆盖堆叠结构，然后电介质层被回蚀刻，并且介电层的一部分保留在堆叠结构上。使用剩余电介质层的一部分作为掩模，去除第一导电层的一部分。在第一导电层上依次形成层间电介质层和第二导电层。由于使用自对准工艺来定义浮动栅极，并且浮栅具有窄顶/宽底部配置，因此简化了制造工艺，并且增加了堆叠栅极的耦合比。

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