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41. 发明授权

US07486683B2 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US07486683B2
公开(公告)日：2009-02-03
申请号：US10894681
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制内尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

42. 发明授权

US07272522B2 Method and systems for optimizing high-speed signal transmission 失效
标题翻译：用于优化高速信号传输的方法和系统
公开(公告)号：US07272522B2
公开(公告)日：2007-09-18
申请号：US11235856
申请日：2005-09-27
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： G01R13/00 , H04B17/00
CPC分类号： H04L25/03343 , H04L1/0001 , H04L1/20 , H04L7/0337 , H04L2025/03375
摘要： A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets of parameter values and the one producing the best signal quality is selected. In a first embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye characterizing the signal behavior, obtained by over-sampling the high-speed received signal. In a second embodiment, the quality of the high-speed received signal is determined by analyzing the behavior of the phase rotator used for data sampling. Finally, in a third embodiment, the quality of the high-speed received signal is determined by analyzing a digital eye, obtained by moving the position of a phase rotator from one end to the other and sampling data at each position.
摘要翻译：公开了一种在同步高速传输系统中自动调整信号发射器参数的方法和系统。根据本发明的方法，对多组参数值分析高速接收信号的质量，并选择产生最佳信号质量的参数值。在第一实施例中，通过分析表征由高速接收信号过采样得到的信号行为的数字眼来确定高速接收信号的质量。在第二实施例中，通过分析用于数据采样的相位旋转器的行为来确定高速接收信号的质量。最后，在第三实施例中，通过分析通过将相位旋转器的位置从一端移动到另一端而获得的数字眼，并且在每个位置处采样数据来确定高速接收信号的质量。

43. 发明授权

US07260145B2 Method and systems for analyzing the quality of high-speed signals 失效
标题翻译：分析高速信号质量的方法和系统
公开(公告)号：US07260145B2
公开(公告)日：2007-08-21
申请号：US10697495
申请日：2003-10-30
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： H04L1/20
摘要： A method and systems for analyzing the quality of high-speed signals, when signals can not be over-sampled due to sampler clock rates, is disclosed. According to the method of the invention, the position of a phase rotator is moved from one end to the other and data are sampled at each position (500). Then, data are formatted (505) to obtain a global value characterizing the signal behavior. Finally, this global value is corrected (510) to remove signal transition falsely detected too early. The use of the phase rotator multiplies artificially the number of sampling positions.
摘要翻译：公开了一种用于分析高速信号的质量的方法和系统，当信号由于采样器时钟速率而不能被过采样时。根据本发明的方法，相位旋转器的位置从一端移动到另一端，并在每个位置（500）采样数据。然后，数据被格式化（505）以获得表征信号行为的全局值。最后，这个全局值得到纠正（510），以消除过早的错误检测信号。使用相位旋转器人工乘以采样位置的数量。

44. 发明申请

US20060251124A1 Method and arrangement for local sychronization in master-slave distributed communication systems 失效
标题翻译：主从分布式通信系统中本地同步的方法和布置
公开(公告)号：US20060251124A1
公开(公告)日：2006-11-09
申请号：US10512671
申请日：2003-03-31
申请人： Michel Colmant , Alan Benner , Francois Abel , Michel Poret , Norhert Schumacher , Alain Blanc , Mark Verhappen , Mitch Gusat
发明人： Michel Colmant , Alan Benner , Francois Abel , Michel Poret , Norhert Schumacher , Alain Blanc , Mark Verhappen , Mitch Gusat
IPC分类号： H04J3/06
CPC分类号： H04L49/153 , H04L49/254 , H04L49/3009 , H04L49/3072 , H04L49/3081 , H04L49/45
摘要： For switching or transmitting data packets, one can provide communication systems which consist of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master (21), the others are slave modules (22) controlled by control signals (25) derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
摘要翻译：对于切换或传输数据分组，可以提供由多个模块组成的通信系统 - 在分组的分段上并行操作 - 以提高速度和处理能力。一个模块作为主机（21），其他模块是由主模块导出的控制信号（25）控制的从模块（22）。重要的是，在每个模块中，数据段和每个分组的相应控制信号被正确同步，因为在大系统中，承载分组段和控制信号路径的数据路径可能具有显着不同的延迟。本发明提供了传播延迟差的测量和用于在每个从模块中引入受控延迟，使得数据段和控制信号可以通过延迟其中一个或另一个来正确地相关。同步数据包除正常数据包之外传输，用于获取用于确定延迟差的时间戳。

45. 发明授权

US06982956B2 System and method for controlling communications network traffic through phased discard strategy selection 失效
标题翻译：通过分阶段淘汰战略选择来控制通信网络流量的系统和方法
公开(公告)号：US06982956B2
公开(公告)日：2006-01-03
申请号：US09843315
申请日：2001-04-25
申请人： Alain Blanc , Francois LeMaut
发明人： Alain Blanc , Francois LeMaut
IPC分类号： H04L12/56
CPC分类号： H04L47/32 , H04L47/10 , H04L47/30
摘要： Congestion at an output from a node in a packet data communications network is controlled by maintaining a traffic profile based on the discardability/priority characteristics of recently received packets and by selecting at least an initial discard strategy which should be effective in ending congestion based on that profile. The profile is established by maintaining counts of the number of packets actually stored in an output buffer and of the number of packets which would have been stored if different discard strategies had been in force. The relationship of certain of the count values to a threshold determines which discard strategy is initially selected. Different, successively less intrusive discard strategies can be implemented until the congestion ends.
摘要翻译：通过基于最近接收到的分组的可丢弃性/优先级特性来保持流量简档，并通过选择至少应该有效的终止拥塞的初始丢弃策略来控制来自分组数据通信网络中的节点的输出的拥塞。个人资料通过维持实际存储在输出缓冲器中的分组数量的计数以及如果不同的丢弃策略已经生效，则将存储的分组数量建立该简档。某些计数值与阈值的关系决定了哪种丢弃策略最初被选择。可以实施不同的，相对较少的侵入性丢弃策略，直到拥塞结束。

46. 发明申请

US20050053078A1 Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's 失效
标题翻译：用于从收缩的VOQ数组中选择确认的算法和系统
公开(公告)号：US20050053078A1
公开(公告)日：2005-03-10
申请号：US10894681
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制中尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

47. 发明授权

US06683854B1 System for checking data integrity in a high speed packet switching network node 失效
标题翻译：用于检查高速分组交换网络节点中的数据完整性的系统
公开(公告)号：US06683854B1
公开(公告)日：2004-01-27
申请号：US09271953
申请日：1999-03-18
申请人： Alain Blanc , Patrick Jeanniot , Alain Pinzaglia
发明人： Alain Blanc , Patrick Jeanniot , Alain Pinzaglia
IPC分类号： H04L100
CPC分类号： H04L1/24
摘要： A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.
摘要翻译：一种用于检查高速分组交换网络节点中的交换单元中的数据传输的完整性的系统，其中通过将数据从第一移位寄存器同时移位到目标设备移位寄存器来执行多播。器件寄存器的输出反馈到第一移位寄存器。检查系统包括用于通过一组选择线选择目标的装置选择电路和一个负或门电路。选择线信号和第一寄存器输出是或门的输入，其输出被反馈到第一寄存器。比较器电路具有由器件选择线和器件寄存器的输出提供的输入。处理器将第一寄存器的内容与逻辑比较器电路的输出进行比较，以测试数据是否已正确组播到目标。

48. 发明授权

US06584124B1 Method and system for accessing ports of a fixed-size cell switch 有权
标题翻译：用于访问固定大小小区交换机端口的方法和系统
公开(公告)号：US06584124B1
公开(公告)日：2003-06-24
申请号：US09304680
申请日：1999-05-04
申请人： Alain Blanc , Rene Glaise
发明人： Alain Blanc , Rene Glaise
IPC分类号： H04J314
CPC分类号： H04L49/3081 , H04L7/048 , H04L12/5601 , H04L49/1553 , H04L2007/045 , H04L2012/5674
摘要： The invention provides a method and system for accessing ports of a very high-speed, fixed-size cell switch fabric. It is aimed at permitting a tradeoff between the overall number of I/Os required to access all the switch ports, that must stay within the board and modules packaging constraints and the maximum speed at which each individual wire, making up ports, may be toggled while not violating any of the speed limitation imposed by the transmission medium (board wiring) or the module interface devices; i.e., receivers and drivers. This is achieved by eliminating the need of having extra control signals, thus, greatly easing the requirement for module and board I/Os. Then, synchronization is obtained from in-band information transported by fixed-size idle logical units from a robust protocol based on two CRCs. The acquisition of synchronization does not require any particular training sequence and is conducted by the receiving device component only which retrieves computed delimiters on which it locks. The method does not assume any overhead and is obtained from the extra bandwidth available while no minimum is ever required after synchronization has been acquired.
摘要翻译：本发明提供一种用于访问非常高速，固定大小小区交换结构的端口的方法和系统。它旨在允许访问所有交换机端口所需的I / O总数之间的权衡，这些权限必须停留在电路板和模块封装约束之内，并且组成端口的每个单独电线的最大速度可能会被切换同时不违反传输介质（电路板接线）或模块接口设备施加的速度限制; 即接收器和驱动器。这是通过消除对额外的控制信号的需要而实现的，从而大大减轻了模块和板I / O的需求。然后，从基于两个CRC的稳健协议的固定大小的空闲逻辑单元传送的带内信息中获得同步。获取同步不需要任何特定的训练序列，仅由接收设备组件执行，检索其锁定的计算分隔符。该方法不承担任何开销，并且可以从可用的额外带宽获得，而在获取同步之后不需要最小值。

49. 发明授权

US06411599B1 Fault tolerant switching architecture 失效
标题翻译：容错交换架构
公开(公告)号：US06411599B1
公开(公告)日：2002-06-25
申请号：US09204394
申请日：1998-12-02
申请人： Alain Blanc , Sylvie Gohl , Michel Poret
发明人： Alain Blanc , Sylvie Gohl , Michel Poret
IPC分类号： H04L122
CPC分类号： H04L49/557 , H04L1/22 , H04L12/5601 , H04L49/103 , H04L49/30 , H04L49/45 , H04L2012/5627
摘要： A fault tolerant switching architecture is provided with two separate switch fabrics each having a switch cure located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element has both a SCAL receive element and a SCAL transmit element for access to a corresponding input and output port of the swatch core. A set of port adapters is distributed at different physical areas, with each connected switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive cells from either one of the switch cores. Each switch fabric can detect an internal breakdown condition occurring in one of its element and send an error control signal to the peer element located in the other switch fabric. Each switch core extracts the Switch Routing Header (SRH) from the cells entering the switch core, and a routing table for obtaining a bit map value that indicates the output ports to which the cell should be routed. An additional controllable masking mechanism is used for altering the value of the bit map in response to the detection of the error control signal from the peer switch core. The routing process is then performed with the altered value of the bitmap.
摘要翻译：具有两个单独的交换结构的容错交换体系结构，每个开关结构具有位于集中式建筑物中的开关固化和分布在不同物理区域中的一组SCAL元件。每个SCAL元件都具有SCAL接收元件和SCAL传输元件，用于访问样本核心的相应输入和输出端口。一组端口适配器分布在不同的物理区域，每个连接的交换结构经由特定的SCAL元件，使得每个交换机核心接收来自任何端口适配器的单元序列，并且相反，任何端口适配器可以接收来自开关核心。每个交换结构可以检测在其元件之一中发生的内部故障状况，并向位于另一个交换结构中的对等元件发送错误控制信号。每个交换机核心从进入交换机核心的小区提取交换路由报头（SRH），以及路由表，用于获取指示该小区应路由的输出端口的位图值。响应于来自对等交换机核心的错误控制信号的检测，使用附加的可控掩蔽机制来改变位图的值。然后使用位图的改变值执行路由过程。

50. 发明授权

US06343081B1 Method and apparatus for managing contention in a self-routing switching architecture in a port expansion mode 失效
标题翻译：用于在端口扩展模式中管理自路由交换架构中的竞争的方法和装置
公开(公告)号：US06343081B1
公开(公告)日：2002-01-29
申请号：US09121992
申请日：1998-07-24
申请人： Alain Blanc , Bernard Brezzo , Pierre Debord , Patrick Jeanniot , Alain Saurel
发明人： Alain Blanc , Bernard Brezzo , Pierre Debord , Patrick Jeanniot , Alain Saurel
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L12/5601 , H04L49/1507 , H04L49/1553 , H04L49/201 , H04L49/25 , H04L49/506 , H04L2012/5679
摘要： A method and apparatus for managing contention in a self-routing switching architecture based on a set of n×n individual switching structures that are connected in a port expansion mode by means of fan-out and fan-in circuits providing access of the Switch Core Access Layer (SCAL) to the different input and output ports of the switching core. The fan-in circuits use an arbitration mechanism for providing a token to the switch that is allowed to deliver the next cell and the arbiter operates from a detection of a special comma character in accordance with the 8B/10B coding scheme which is introduced in the data flow between the individual switching structures and the fan-in circuits. This provides a compensation for the difference in transfer delays of the cells even when high switching speed and long length of the physical media are involved.
摘要翻译：一种用于管理自路由交换架构中的争用的方法和装置，所述方法和装置基于通过扇出方式连接的端口扩展模式的一组nxn个别交换结构，以及提供交换机核心接入层（SCAL）到交换核心的不同输入和输出端口。扇入电路使用仲裁机制，用于向交换机提供令牌，该令牌被允许传送下一个小区，并且仲裁器根据在8B中引入的8B / 10B编码方案的特殊逗号字符的检测来操作各个开关结构和扇入电路之间的数据流。即使涉及物理介质的高切换速度和长的长度，这也为单元的传送延迟的差异提供了补偿。

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