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    • 1. 发明授权
    • System for checking data integrity in a high speed packet switching network node
    • 用于检查高速分组交换网络节点中的数据完整性的系统
    • US06683854B1
    • 2004-01-27
    • US09271953
    • 1999-03-18
    • Alain BlancPatrick JeanniotAlain Pinzaglia
    • Alain BlancPatrick JeanniotAlain Pinzaglia
    • H04L100
    • H04L1/24
    • A system for checking the integrity of data transfer in a switching element in a high speed packet switching network node where multicasting is performed by simultaneously shifting data from a first shift register into the targeted device shift registers. The outputs of the device registers are fed back into the first shift register. The checking system includes a device select circuit for selecting the targeted via a set of select lines and a negative OR gate circuit. The select line signals and the first register output are inputs to the OR gate, the output of which is fed back to the first register. A comparator circuit has inputs supplied by the device select lines and the outputs of the device registers. A processor compares the contents of the first register to the outputs from the logic comparator circuit to test whether the data has been properly multicast to the targeted.
    • 一种用于检查高速分组交换网络节点中的交换单元中的数据传输的完整性的系统,其中通过将数据从第一移位寄存器同时移位到目标设备移位寄存器来执行多播。 器件寄存器的输出反馈到第一移位寄存器。 检查系统包括用于通过一组选择线选择目标的装置选择电路和一个负或门电路。 选择线信号和第一寄存器输出是或门的输入,其输出被反馈到第一寄存器。 比较器电路具有由器件选择线和器件寄存器的输出提供的输入。 处理器将第一寄存器的内容与逻辑比较器电路的输出进行比较,以测试数据是否已正确组播到目标。