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41. 发明授权

US06916670B2 Electronic package repair process 失效
标题翻译：电子封装修复过程
公开(公告)号：US06916670B2
公开(公告)日：2005-07-12
申请号：US10358431
申请日：2003-02-04
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H05K3/46 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/00 , H05K3/22 , H01L21/00
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

42. 发明授权

US06823585B2 Method of selective plating on a substrate 失效
标题翻译：在基板上选择性镀覆的方法
公开(公告)号：US06823585B2
公开(公告)日：2004-11-30
申请号：US10249305
申请日：2003-03-28
申请人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
发明人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
IPC分类号： H01R4300
CPC分类号： H05K3/242 , H05K1/0306 , H05K3/0035 , H05K3/048 , H05K3/184 , H05K3/225 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , Y10T29/49721 , Y10T29/49732 , Y10T29/49737 , Y10T29/49746
摘要： A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
摘要翻译：在基板上形成表面电镀金属化的方法和结构。将两层胶带施加到基材的表面。通过暴露衬底表面的两层带切割第一路径。第一路径在衬底的顶表面上连接至少一个导电通孔。通过暴露第一层胶带的第二层胶带切割第二条路径。第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。去除胶带时，去除牺牲路径。

43. 发明授权

US6060176A Corrosion protection for metallic features 失效
标题翻译：金属特性的防腐蚀
公开(公告)号：US6060176A
公开(公告)日：2000-05-09
申请号：US936750
申请日：1997-09-25
申请人： Krystyna W. Semkow , Eugene J. O'Sullivan
发明人： Krystyna W. Semkow , Eugene J. O'Sullivan
IPC分类号： C23C18/16 , C23C18/36 , H01L21/288 , H01L21/48 , H01L21/768 , B32B3/00 , H01L29/12
CPC分类号： C23C18/36 , C23C18/161 , C23C18/165 , H01L21/288 , H01L21/4846 , H01L21/76838 , Y10S428/936 , Y10T428/12528 , Y10T428/12549 , Y10T428/12569 , Y10T428/12861 , Y10T428/12875 , Y10T428/12944 , Y10T428/24917
摘要： A microelectronic structure, having 1) at least one metallic feature situated on a layer of material selected from the group consisting of nonmetallic and semiconductor materials; 2) a layer of a cobalt-phosphorus alloy (Co(P)) covering at least one of the at least one metallic feature; and 3) a layer of a material selected from the group consisting of nickel and palladium covering the area covered by the Co(P) layer.
摘要翻译：一种微电子结构，具有1）位于选自非金属和半导体材料的材料层上的至少一个金属特征; 2）覆盖至少一个金属特征中的至少一个的钴 - 磷合金层（Co（P））层; 和3）选自由覆盖由Co（P）层覆盖的区域的镍和钯组成的组中的材料层。

44. 发明授权

US5108562A Electrolytic method for forming vias and through holes in copper-invar-copper core structures 失效
标题翻译：用于在铜 - 铜 - 铜芯结构中形成通孔和通孔的电解方法
公开(公告)号：US5108562A
公开(公告)日：1992-04-28
申请号：US651175
申请日：1991-02-06
申请人： Peter J. Duke , Leann G. Keim , Krystyna W. Semkow
发明人： Peter J. Duke , Leann G. Keim , Krystyna W. Semkow
IPC分类号： C25F3/02 , C25F3/12 , H01L21/3063 , H01L21/48 , H01L23/14 , H05K3/00 , H05K3/06 , H05K3/07 , H05K3/44
CPC分类号： C25F3/12 , H01L21/4803 , H01L23/142 , H05K3/44 , H01L2924/0002 , H05K2201/0338 , H05K2201/068 , H05K2203/0323 , H05K2203/0361 , H05K2203/1184 , H05K3/062 , H05K3/067 , H05K3/07
摘要： Disclosed is a method of fabricating a microelectronic package having least one layer formed of a Cu-Invar-Cu core encapsulated between a pair of dielectric films. The package is intended to carry surface circuitization on an external surface, with internal circuitization from the surface circuitization passing through the core. The method includes contacting the copper within the Cu-Invar-Cu core with a copper etching aqueous solution of a strong base and a strong oxidizing acid, while maintaining the copper anodic. This electrolytically converts the copper to soluble copper oxides. In a separate step the Invar of the Cu-Invar-Cu core is electrolytically etched with an Invar etching aqueous solution of sodium chloride. This step is carried out under conditions to electrolytically form soluble iron and nickel chlorides while passivating the copper.

45. 发明授权

US5098533A Electrolytic method for the etch back of encapsulated copper-Invar-copper core structures 失效
标题翻译：封装的铜 - 堇青铜核心结构的回蚀电解方法
公开(公告)号：US5098533A
公开(公告)日：1992-03-24
申请号：US651073
申请日：1991-02-06
申请人： Peter J. Duke , Krystyna W. Semkow
发明人： Peter J. Duke , Krystyna W. Semkow
IPC分类号： C25F3/02 , H01L21/48 , H05K3/06 , H05K3/07 , H05K3/44
CPC分类号： H05K3/44 , H01L21/4803 , H01L21/486 , H05K2201/0338 , H05K2201/068 , H05K2203/0285 , H05K2203/0323 , H05K2203/1184 , H05K3/062 , H05K3/07 , H05K3/445
摘要： Disclosed is a method of fabricating a microelectronic package having least one layer formed of a copper-Invar-copper core encapsulated between a pair of dielectric films. The method includes exposing a copper-Invar-copper surface of the copper-Invar-copper core, for example, exposing an edge of the copper-Invar-copper core or drilling a whole through the layer to expose internal copper-Invar-copper. The copper-Invar-copper is then shaped, that is, back etched. This is an electrolytic process where the package is immersed in a substantially pH neutral electrolyte including a counter- electrode. A preferred electrolyte is an aqueous alkali metal nitrate solution. The electrolyte wets the exposed surface of said copper-Invar-copper core. The exposed surface of the copper-Invar-copper core is rendered anodic with respect to the counter-electrode and an electrical potential is applied therebetween. This results in electrochemically etching and shaping the copper-Invar-copper surface.
摘要翻译：公开了一种制造微电子封装的方法，该微电子封装具有封装在一对电介质膜之间的由铜 - 英巴铜芯形成的至少一层。该方法包括将铜 - Inv铜 - 铜芯的铜 - Inv铜 - 铜表面暴露出来，例如，暴露出铜 - Inv铜 - 铜芯的边缘，或者穿过该层进行整体钻孔以暴露内部铜 - Inv铜。然后将铜 - 殷铜铜成形，即后蚀刻。这是一种电解方法，其中将封装浸入包括反电极的基本上pH中性的电解质中。优选的电解质是碱金属硝酸盐水溶液。电解液润湿所述铜 - Inv铜 - 铜芯的暴露表面。铜 - 铱铜芯的暴露表面相对于反电极呈阳极，并且在其间施加电位。这导致电化学蚀刻和成形铜 - 阴极铜表面。

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