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41. 发明申请

US20070047364A1 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 审中-公开
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US20070047364A1
公开(公告)日：2007-03-01
申请号：US11216666
申请日：2005-08-31
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

42. 发明申请

US20070040621A1 Voltage controlled oscillator using dual gated asymmetrical FET devices 审中-公开
标题翻译：使用双门控不对称FET器件的压控振荡器
公开(公告)号：US20070040621A1
公开(公告)日：2007-02-22
申请号：US11204412
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.
摘要翻译：使用由不对称双门控FET（ADG-FET）器件配置的反相级形成环形振荡器。最简单的形式使用由ADG-PFET和ADG-NFET配置的奇数CMOS反相器级。前门用作逻辑输入，并连接到主环的前一个输出。 ADG-PFET器件的背栅极耦合到第一控制电压，并且ADG-NFET器件的背栅极耦合到作为基于偏移电压的第一控制电压的补码的第二控制电压。也可以使用使用ADG-FET器件的逻辑反相级的其它配置。改变控制电压以调制由耦合到前门的输入端处的逻辑状态设置的电流电平。

43. 发明申请

US20060290383A1 Dual gate dynamic logic 有权
标题翻译：双门动态逻辑
公开(公告)号：US20060290383A1
公开(公告)日：2006-12-28
申请号：US11168692
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

44. 发明申请

US20060232321A1 High-density low-power data retention power gating with double-gate devices 有权
标题翻译：具有双栅极器件的高密度低功耗数据保持功率门控
公开(公告)号：US20060232321A1
公开(公告)日：2006-10-19
申请号：US11106913
申请日：2005-04-15
申请人： Ching-Te Chuang , Koushik Das , Keunwoo Kim
发明人： Ching-Te Chuang , Koushik Das , Keunwoo Kim
IPC分类号： H03K17/687
CPC分类号： H01L27/105 , G11C5/14 , H01L27/11 , H01L27/1116 , H01L29/785 , H01L29/78648 , H03K3/356156
摘要： A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.
摘要翻译：具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。还提出了拟议方案的虚拟供应/地面反弹分析。

45. 发明授权

US09454629B2 Fet-bounding for fast TCAD-based variation modeling 有权
标题翻译：快速基于TCAD的变异建模
公开(公告)号：US09454629B2
公开(公告)日：2016-09-27
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

46. 发明授权

US08849643B2 Table-lookup-based models for yield analysis acceleration 有权
标题翻译：基于表查找的产量分析加速模型
公开(公告)号：US08849643B2
公开(公告)日：2014-09-30
申请号：US13107355
申请日：2011-05-13
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.
摘要翻译：在一个实施例中，本发明是用于产量分析加速的基于表查找的模型的方法和装置。用于统计评估集成电路的设计的方法的一个实施例包括模拟集成电路并产生用于模拟的查找表，所述查找表包括指定相关偏置电压的器件元件的一个或多个块，其中该生成包括仅生成在模拟期间所需的偏置电压指定该器件元件的一个或多个块的那些块。

47. 发明授权

US08352230B2 Integrated framework for finite-element methods for package, device and circuit co-design 有权
标题翻译：用于封装，器件和电路协同设计的有限元方法的集成框架
公开(公告)号：US08352230B2
公开(公告)日：2013-01-08
申请号：US12723130
申请日：2010-03-12
申请人： Keunwoo Kim , Soojae Park
发明人： Keunwoo Kim , Soojae Park
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/50 , G06F17/5018 , G06F17/5036 , G06F2217/40 , G06F2217/78 , G06F2217/80
摘要： Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations.
摘要翻译：电气有限元分析在包括设备的电路设计中进行，以确定可接受的功率性能包络并获得电路温度映射的数据。基于电路温度映射的数据，开发了电路设计的电路温度图。基于电路温度图对电路设计的封装设计进行热机械有限元分析，以确定基于热应力考虑的封装可靠性限制。确定包装设计和电路设计是否共同满足：（i）在可接受的功率性能包络中指定的功率性能条件; 和（ii）基于热应力考虑的封装可靠性限制。

48. 发明授权

US07903450B2 Asymmetrical memory cells and memories using the cells 有权
标题翻译：不对称存储单元和使用单元的存储器
公开(公告)号：US07903450B2
公开(公告)日：2011-03-08
申请号：US12040966
申请日：2008-03-03
申请人： Ching-Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching-Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.
摘要翻译：通过提供改进的读取稳定性和改进的写入性能和余量的一个或多个来改进非对称SRAM单元。第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

49. 发明申请

US20100195373A1 Method of Operating a Memory Circuit using Memory Cells with Independent-Gate Controlled Access Devices 有权
标题翻译：使用具有独立门控制访问设备的存储单元操作存储器电路的方法
公开(公告)号：US20100195373A1
公开(公告)日：2010-08-05
申请号：US12757648
申请日：2010-04-09
申请人： Keunwoo Kim
发明人： Keunwoo Kim
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C11/412 , H01L29/7855
摘要： A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON.”
摘要翻译：存储单元包括被配置为选择性地将交叉耦合的反相器与真和互补位线互连的双栅极第一和第二存取器件。每个访问设备具有连接到READ字线的第一栅极和连接到WRITE字线的第二栅极。在READ操作期间，第一和第二访问设备被配置为在双门下拉设备被配置为操作的情况下以READ字线“ON”和WRITE字线“OFF”的单栅极模式操作在双门模式下。在写入操作期间，第一和第二存取设备被配置为在READ字线“ON”并且WRITE字线也为“ON”的双门模式下工作。

50. 发明授权

US07681628B2 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅极偏置的动态控制
公开(公告)号：US07681628B2
公开(公告)日：2010-03-23
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

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