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1. 发明申请

US20070040584A1 Dual-gate dynamic logic circuit with pre-charge keeper 有权
公开(公告)号：US20070040584A1
公开(公告)日：2007-02-22
申请号：US11204401
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

2. 发明申请

US20070047364A1 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 审中-公开
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US20070047364A1
公开(公告)日：2007-03-01
申请号：US11216666
申请日：2005-08-31
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

3. 发明申请

US20070040621A1 Voltage controlled oscillator using dual gated asymmetrical FET devices 审中-公开
标题翻译：使用双门控不对称FET器件的压控振荡器
公开(公告)号：US20070040621A1
公开(公告)日：2007-02-22
申请号：US11204412
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.
摘要翻译：使用由不对称双门控FET（ADG-FET）器件配置的反相级形成环形振荡器。最简单的形式使用由ADG-PFET和ADG-NFET配置的奇数CMOS反相器级。前门用作逻辑输入，并连接到主环的前一个输出。 ADG-PFET器件的背栅极耦合到第一控制电压，并且ADG-NFET器件的背栅极耦合到作为基于偏移电压的第一控制电压的补码的第二控制电压。也可以使用使用ADG-FET器件的逻辑反相级的其它配置。改变控制电压以调制由耦合到前门的输入端处的逻辑状态设置的电流电平。

4. 发明申请

US20060290384A1 Independent gate control logic circuitry 失效
标题翻译：独立门控逻辑电路
公开(公告)号：US20060290384A1
公开(公告)日：2006-12-28
申请号：US11168717
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FET device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FET device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.
摘要翻译：动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点逻辑输入的布尔组合。逻辑树具有堆叠配置，其具有至少一个多栅极FET器件，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点时钟信号的相位。多栅极FET器件具有耦合到第一逻辑输入的一个栅极和耦合到用于预充电动态节点的时钟信号的补码的第二栅极。

5. 发明申请

US20060290383A1 Dual gate dynamic logic 有权
标题翻译：双门动态逻辑
公开(公告)号：US20060290383A1
公开(公告)日：2006-12-28
申请号：US11168692
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

6. 发明申请

US20070046323A1 Control circuitry for power gating virtual power supply rails at differing voltage potentials 失效
公开(公告)号：US20070046323A1
公开(公告)日：2007-03-01
申请号：US11211954
申请日：2005-08-25
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K17/16
CPC分类号： H03K19/0016
摘要： A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

7. 发明申请

US20060055391A1 Power-gating cell for virtual power rail control 有权
标题翻译：用于虚拟电源轨控制的电源门控单元
公开(公告)号：US20060055391A1
公开(公告)日：2006-03-16
申请号：US10926597
申请日：2004-08-26
申请人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
IPC分类号： F02P3/02
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译：虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。控制信号在单元边界被锁存或响应于时钟信号锁存。

8. 发明申请

US20060033531A1 Circuit for controlling leakage 有权
标题翻译：电路用于控制泄漏
公开(公告)号：US20060033531A1
公开(公告)日：2006-02-16
申请号：US10916980
申请日：2004-08-12
申请人： Hung Ngo , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/094
CPC分类号： H03K17/167 , H03K19/0016
摘要： Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials of the power supply from circuitry with large high leakage devices. Driver circuits comprise a low leakage logic path for holding logic states of the output. A high leakage logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each high leakage path that enhances the current drive of a logic state on the output are leakage stress relieved by allowing their drive inputs to collapse after the output logic state has been asserted. The high leakage logic paths employ multiple stages with collapsing logic states that are generated in response to asserted logic states on the output and logic states of the low leakage logic path thus reducing the device sizes needed to control leakage.
摘要翻译：逻辑电路中的泄漏电流通过将电源的电压电压与具有大的高泄漏器件的电路耦合和去耦来进行管理。驱动器电路包括用于保持输出的逻辑状态的低泄漏逻辑路径。使用与低泄漏逻辑路径并联的高泄漏逻辑路径来断言从输入到输出的正向的每个逻辑状态。在每个高泄漏路径中的大输出设备，增强了输出上的逻辑状态的电流驱动，通过允许其驱动输入在输出逻辑状态被置位之后崩溃而消除泄漏应力。高泄漏逻辑路径采用多级，其具有响应于低泄漏逻辑路径的输出和逻辑状态上的断言逻辑状态产生的折叠逻辑状态，从而减少了控制泄漏所需的器件尺寸。

9. 发明申请

US20050225355A1 Interface circuit for coupling between logic circuit domains 失效
标题翻译：用于在逻辑电路域之间耦合的接口电路
公开(公告)号：US20050225355A1
公开(公告)日：2005-10-13
申请号：US10821047
申请日：2004-04-08
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K3/00 , H03K3/356 , H03K19/00 , H03K19/0175 , H03K19/0185
CPC分类号： H03K3/356008 , H03K19/0016 , H03K19/018521
摘要： CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where circuitry does not have power supply gating. Each output that couples signals from one logic circuit domain to another logic circuit is interfaced with a C_driver and a S_keeper which automatically assure that the output state is held when circuitry is power-gated put to reduce leakage power. The S_keeper and C_driver have low leakage circuits that maintain signal states and are not used for high speed operation.
摘要翻译： CMOS电路分为第一和第二逻辑电路域。第一逻辑电路域可以是可选择的可切割域（C_Domain），其中电路具有电源选通以减少泄漏功率和电路不具有电源门控的不可切割域（NC_Domain）。将信号从一个逻辑电路域耦合到另一个逻辑电路的每个输出端与C_driver和S_keeper接口，该电路可以自动确保在电路门控电源降低漏电功率时保持输出状态。 S_keeper和C_driver具有低泄漏电路，保持信号状态，不用于高速运行。

10. 发明申请

US20070237012A1 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance 有权
标题翻译：级联测试电路采用位线驱动器件，用于评估存储单元性能
公开(公告)号：US20070237012A1
公开(公告)日：2007-10-11
申请号：US11250061
申请日：2005-10-13
申请人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：具有用于评估存储器单元性能的位线驱动装置的级联测试电路在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

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