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41. 发明申请

US20100015814A1 MOSFET Device With Localized Stressor 有权
标题翻译：具有局部应力的MOSFET器件
公开(公告)号：US20100015814A1
公开(公告)日：2010-01-21
申请号：US12176655
申请日：2008-07-21
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/31
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
摘要翻译：提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。应力诱导层可以是凹陷区域或非凹陷区域。第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

42. 发明授权

US07335544B2 Method of making MOSFET device with localized stressor 有权
标题翻译：制造具有局部应力源的MOSFET器件的方法
公开(公告)号：US07335544B2
公开(公告)日：2008-02-26
申请号：US11012413
申请日：2004-12-15
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源极/漏极区的晶体管，在栅电极和源极/漏极区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

43. 发明授权

US07327009B2 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US07327009B2
公开(公告)日：2008-02-05
申请号：US11620085
申请日：2007-01-05
申请人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L29/00
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

44. 发明授权

US07232730B2 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US07232730B2
公开(公告)日：2007-06-19
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善其相应的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

45. 发明申请

US20070105337A1 SELECTIVE NITRIDE LINER FORMATION FOR SHALLOW TRENCH ISOLATION 有权
标题翻译：选择性氮化物衬里形成用于浅层分离
公开(公告)号：US20070105337A1
公开(公告)日：2007-05-10
申请号：US11620085
申请日：2007-01-05
申请人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

46. 发明申请

US20070063282A1 SOI-like structures in a bulk semiconductor substrate 审中-公开
标题翻译：体半导体衬底中的SOI类结构
公开(公告)号：US20070063282A1
公开(公告)日：2007-03-22
申请号：US11599931
申请日：2006-11-15
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L27/12 , H01L29/00
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

47. 发明授权

US07166525B2 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US07166525B2
公开(公告)日：2007-01-23
申请号：US10758317
申请日：2004-01-15
申请人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

48. 发明申请

US20060223255A1 Method for selectively stressing MOSFETs to improve charge carrier mobility 审中-公开
标题翻译：选择性地强迫MOSFET以改善载流子迁移率的方法
公开(公告)号：US20060223255A1
公开(公告)日：2006-10-05
申请号：US11370397
申请日：2006-03-07
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

49. 发明申请

US20060183292A1 STI liner modification method 有权
标题翻译： STI衬垫修改方法
公开(公告)号：US20060183292A1
公开(公告)日：2006-08-17
申请号：US11059728
申请日：2005-02-17
申请人： Chien-Hao Chen , Vincent Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

50. 发明授权

US08673736B2 Method of forming SOI-like structure in a bulk semiconductor substrate by annealing a lower portion of a trench while protecting an upper portion of the trench 有权
标题翻译：通过在保护沟槽的上部的同时退火沟槽的下部来在体半导体衬底中形成SOI样结构的方法
公开(公告)号：US08673736B2
公开(公告)日：2014-03-18
申请号：US11546768
申请日：2006-10-12
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

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