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41. 发明授权

US08835291B2 Strained gate electrodes in semiconductor devices 有权
标题翻译：半导体器件中的应变栅电极
公开(公告)号：US08835291B2
公开(公告)日：2014-09-16
申请号：US12404050
申请日：2009-03-13
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842
摘要： Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.
摘要翻译：本发明的实施例提供一种半导体器件和制造方法。制造MOS器件及其多晶或非晶栅电极，使得栅电极内的本征应力在MOS源/漏区之间的沟道区产生应力。实施例包括在将中间NMOS栅极电极层的一部分转换成非晶层之后形成NMOS器件和PMOS器件，然后在图案化之前将其重结晶以形成电极。 NMOS再结晶栅电极中的平均晶粒尺寸小于PMOS再结晶栅电极中的平均晶粒尺寸。在另一实施例中，NMOS器件包括非晶栅电极。

42. 发明授权

US08120767B2 Mask making decision for manufacturing (DFM) on mask quality control 有权
标题翻译：面罩制作决策（DFM）对面罩质量控制
公开(公告)号：US08120767B2
公开(公告)日：2012-02-21
申请号：US12048043
申请日：2008-03-13
申请人： Chih-Chiang Tu , Chien-Chao Huang
发明人： Chih-Chiang Tu , Chien-Chao Huang
IPC分类号： G01N21/00 , G06K9/00
CPC分类号： G03F1/84
摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
摘要翻译：本公开提供了一种制造掩模的方法。该方法包括将多个模式特征分配给不同的数据类型; 在掩模上写入多个图案特征; 根据分配的数据类型检查具有不同检查灵敏度的多个图案特征; 以及根据所述多个图案特征的检查来修复所述掩模上的所述多个图案特征。

43. 发明授权

US08008157B2 CMOS device with raised source and drain regions 有权
标题翻译： CMOS器件具有升高的源极和漏极区域
公开(公告)号：US08008157B2
公开(公告)日：2011-08-30
申请号：US11588920
申请日：2006-10-27
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.
摘要翻译：形成半导体结构的方法包括形成PMOS器件和NMOS器件。形成PMOS器件的步骤包括在半导体衬底上形成第一栅叠层; 在所述第一栅极堆叠的侧壁上形成第一偏移间隔物; 使用第一偏移间隔件作为掩模在半导体衬底中形成应力器; 并且在应激源上外延生长第一升高的源极/漏极延伸（LDD）区域。形成NMOS器件的步骤包括在半导体衬底上形成第二栅极叠层; 在所述第二栅极堆叠的侧壁上形成第二偏移间隔物; 使用第二偏移间隔物作为掩模在半导体衬底上外延生长第二隆起的LDD区; 以及形成与第二凸起LDD区域相邻的深源极/漏极区域。

44. 发明授权

US07871742B2 Method for controlling phase angle of a mask by post-treatment 有权
标题翻译：通过后处理控制面罩的相位角的方法
公开(公告)号：US07871742B2
公开(公告)日：2011-01-18
申请号：US11697015
申请日：2007-04-05
申请人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
发明人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
IPC分类号： G03F1/00
CPC分类号： G03F1/26 , G03F1/32
摘要： A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.
摘要翻译：提供了一种用于控制掩模的相位角的方法。形成包括基板和吸收体的掩模。对掩模进行含氮等离子体处理以减小相位角。或者，对掩模进行含氮等离子体处理，然后进行真空紫外线处理，以在掩模上形成钝化层。

45. 发明授权

US07571421B2 System, method, and computer-readable medium for performing data preparation for a mask design 有权
标题翻译：用于执行掩模设计的数据准备的系统，方法和计算机可读介质
公开(公告)号：US07571421B2
公开(公告)日：2009-08-04
申请号：US11738844
申请日：2007-04-23
申请人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
发明人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed.
摘要翻译：提供了一种用于执行数据准备的方法，计算机可读介质和系统。接收集成电路设计，并且调用多个预光学邻近校正处理，使得并行地执行多个预光学邻近校正处理。响应于多个预光学邻近校正处理中的每一个已经完成的确定来调用光学邻近校正处理。响应于光学邻近校正处理已经完成的确定，调用后光学邻近校正处理。

46. 发明申请

US20070235835A1 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US20070235835A1
公开(公告)日：2007-10-11
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

47. 发明授权

US07135372B2 Strained silicon device manufacturing method 有权
公开(公告)号：US07135372B2
公开(公告)日：2006-11-14
申请号：US10937722
申请日：2004-09-09
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

48. 发明授权

US07119440B2 Back end IC wiring with improved electro-migration resistance 有权
标题翻译：后端IC布线具有改善的电迁移电阻
公开(公告)号：US07119440B2
公开(公告)日：2006-10-10
申请号：US10813784
申请日：2004-03-30
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multi-level semiconductor device wiring interconnect structure and method of forming the same to improve electrical properties and reliability of wiring interconnects including an electromigration resistance and electrical resistance, the method including forming a dielectric insulating layer over a conductive portion; forming a via opening in closed communication with the conductive portion; forming a first barrier layer to line the via opening; forming a layer of AlCu according to a sputtering process to fill the via opening to form an AlCu via including a portion overlying the first dielectric insulating layer; and, photolithographically patterning and dry etching the portion to form an AlCu interconnect line over the AlCu via.
摘要翻译：一种多级半导体器件布线互连结构及其形成方法，以改善包括电迁移电阻和电阻的布线互连的电性能和可靠性，所述方法包括在导电部分上形成介电绝缘层; 形成与所述导电部分密封连通的通孔; 形成第一阻挡层以使所述通孔开口; 根据溅射工艺形成AlCu层以填充通孔以形成包含覆盖在第一介电绝缘层上的部分的AlCu; 并且光刻地图案化和干蚀刻该部分以在AlCu通孔上形成AlCu互连线。

49. 发明申请

US20060003520A1 Method for forming semiconductor device with modified channel compressive stress 有权
标题翻译：用于形成具有改变的通道压应力的半导体器件的方法
公开(公告)号：US20060003520A1
公开(公告)日：2006-01-05
申请号：US11219439
申请日：2005-09-02
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.
摘要翻译：用于形成半导体器件的方法提供在衬底的顶部上形成栅极区域。栅极侧壁衬里形成在栅极区域的相对侧上，侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分。嵌入式间隔件形成在侧壁衬套的顶部。垫片下方的侧壁衬套从相应的垫片的边缘被拉回预定的距离。通过减小原来形成的间隔物的高度来形成凹进的间隔物。间隔件的高度低于门侧壁衬套的高度，并且侧壁衬套的水平部分的宽度比间隔件的宽度短。减少的间隔物高度降低了设备通道应力。

50. 发明申请

US20050275043A1 Novel semiconductor device design 审中-公开
标题翻译：新型半导体器件设计
公开(公告)号：US20050275043A1
公开(公告)日：2005-12-15
申请号：US11146692
申请日：2005-06-07
申请人： Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Cheng-Chuan Huang , Tong-Heuan Chung
发明人： Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Cheng-Chuan Huang , Tong-Heuan Chung
IPC分类号： H01L21/768 , H01L27/02 , H01L29/76
CPC分类号： H01L21/76838 , H01L21/76895 , H01L27/0207
摘要： An integrated circuit having small layout area and a method of forming the same are provided. A slant contact is formed by shifting a portion of a contact a distance less than a whole dimension of the contact along the direction shifted. By using slant contacts, the optical proximity effect is reduced, the device density in the integrated circuit is increased and cross talk is reduced. In the preferred embodiment, the slant contact is combined with other techniques such as compound interconnection, butted local interconnection and slim spacers to reduce the layout area. In another embodiments, a six-transistor SRAM cell can be designed with a slant contact, compound interconnection and butted local interconnection to reduce the layout area.
摘要翻译：提供了具有小布局面积的集成电路及其形成方法。通过使触点的一部分沿着移动的方向移动小于接触件的整个尺寸的距离来形成倾斜接触。通过使用倾斜触点，光学邻近效应降低，集成电路中的器件密度增加并且串扰减少。在优选实施例中，倾斜触点与诸如复合互连，对接的局部互连和细长间隔物的其它技术组合以减少布局面积。在另一个实施例中，可以设计六晶体管SRAM单元，其具有倾斜接触，复合互连和对接的局部互连以减小布局面积。

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